Lines Matching full:u3
25 u3 port0 0x0900 U3PHYD
30 u3 port1 0x1100 U3PHYD
42 u3 port0 0x0700 SPLLC
51 u3 port1 0x1700 SPLLC
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are
170 - description: internal R efuse for U2 PHY or U3/PCIe PHY
171 - description: rx_imp_sel efuse for U3/PCIe PHY
172 - description: tx_imp_sel efuse for U3/PCIe PHY
175 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
176 three items should be provided at the same time for U3/PCIe PHY,