Lines Matching +full:phy +full:- +full:ref +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek T-PHY Controller
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 The T-PHY controller supports physical layer functionality for a number of
17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and
18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode:
19 -----------------------------------
67 pattern: "^t-phy@[0-9a-f]+$"
71 - items:
72 - enum:
73 - mediatek,mt2701-tphy
74 - mediatek,mt7623-tphy
75 - mediatek,mt7622-tphy
76 - mediatek,mt8516-tphy
77 - const: mediatek,generic-tphy-v1
78 - items:
79 - enum:
80 - mediatek,mt2712-tphy
81 - mediatek,mt7629-tphy
82 - mediatek,mt8183-tphy
83 - mediatek,mt8186-tphy
84 - mediatek,mt8192-tphy
85 - mediatek,mt8365-tphy
86 - const: mediatek,generic-tphy-v2
87 - items:
88 - enum:
89 - mediatek,mt8188-tphy
90 - mediatek,mt8195-tphy
91 - const: mediatek,generic-tphy-v3
92 - const: mediatek,mt2701-u3phy
94 - const: mediatek,mt2712-u3phy
96 - const: mediatek,mt8173-u3phy
101 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for
102 T-PHY V2/V3, such as mt2712.
105 "#address-cells":
108 "#size-cells":
111 # Used with non-empty value if optional 'reg' is not provided.
113 # (child-bus-address, parent-bus-address, length).
116 mediatek,src-ref-clk-mhz:
121 mediatek,src-coef:
124 $ref: /schemas/types.yaml#/definitions/uint32
129 "^(usb|pcie|sata)-phy@[0-9a-f]+$":
132 A sub-node is required for each port the controller provides.
143 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
144 - description: Reference clock of analog phy
147 separated, otherwise uses "ref" clock only if needed.
149 clock-names:
152 - const: ref
153 - const: da_ref
155 "#phy-cells":
160 - description: The PHY type
162 - PHY_TYPE_USB2
163 - PHY_TYPE_USB3
164 - PHY_TYPE_PCIE
165 - PHY_TYPE_SATA
166 - PHY_TYPE_SGMII
168 nvmem-cells:
170 - description: internal R efuse for U2 PHY or U3/PCIe PHY
171 - description: rx_imp_sel efuse for U3/PCIe PHY
172 - description: tx_imp_sel efuse for U3/PCIe PHY
175 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these
176 three items should be provided at the same time for U3/PCIe PHY,
178 If unspecified, will use hardware auto-load efuse.
180 nvmem-cell-names:
182 - const: intr
183 - const: rx_imp
184 - const: tx_imp
187 mediatek,eye-src:
189 The value of slew rate calibrate (U2 phy)
190 $ref: /schemas/types.yaml#/definitions/uint32
194 mediatek,eye-vrt:
196 The selection of VRT reference voltage (U2 phy)
197 $ref: /schemas/types.yaml#/definitions/uint32
201 mediatek,eye-term:
203 The selection of HS_TX TERM reference voltage (U2 phy)
204 $ref: /schemas/types.yaml#/definitions/uint32
210 The selection of internal resistor (U2 phy)
211 $ref: /schemas/types.yaml#/definitions/uint32
217 The selection of disconnect threshold (U2 phy)
218 $ref: /schemas/types.yaml#/definitions/uint32
222 mediatek,pre-emphasis:
224 The level of pre-emphasis which used to widen the eye opening and
227 8.3% etc. (U2 phy)
228 $ref: /schemas/types.yaml#/definitions/uint32
237 mediatek,syscon-type:
238 $ref: /schemas/types.yaml#/definitions/phandle-array
245 - description:
247 - description:
249 - description:
254 - reg
255 - "#phy-cells"
260 - compatible
261 - "#address-cells"
262 - "#size-cells"
263 - ranges
268 - |
269 #include <dt-bindings/clock/mt8173-clk.h>
270 #include <dt-bindings/interrupt-controller/arm-gic.h>
271 #include <dt-bindings/interrupt-controller/irq.h>
272 #include <dt-bindings/phy/phy.h>
274 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3";
276 reg-names = "mac", "ippc";
282 clock-names = "sys_ck";
285 t-phy@11290000 {
286 compatible = "mediatek,mt8173-u3phy";
288 #address-cells = <1>;
289 #size-cells = <1>;
292 u2port0: usb-phy@11290800 {
295 clock-names = "ref", "da_ref";
296 #phy-cells = <1>;
299 u3port0: usb-phy@11290900 {
302 clock-names = "ref";
303 #phy-cells = <1>;
306 u2port1: usb-phy@11291000 {
308 #phy-cells = <1>;