Lines Matching +full:hdmi +full:- +full:tx +full:- +full:phy
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY binding
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
21 pattern: "^hdmi-phy@[0-9a-f]+$"
25 - items:
26 - enum:
27 - mediatek,mt7623-hdmi-phy
28 - const: mediatek,mt2701-hdmi-phy
29 - const: mediatek,mt2701-hdmi-phy
30 - const: mediatek,mt8173-hdmi-phy
37 - description: PLL reference clock
39 clock-names:
41 - const: pll_ref
43 clock-output-names:
45 - const: hdmitx_dig_cts
47 "#phy-cells":
50 "#clock-cells":
55 TX DRV bias current for < 1.65Gbps
63 TX DRV bias current for >= 1.65Gbps
70 - compatible
71 - reg
72 - clocks
73 - clock-names
74 - clock-output-names
75 - "#phy-cells"
76 - "#clock-cells"
81 - |
82 #include <dt-bindings/clock/mt8173-clk.h>
83 hdmi_phy: hdmi-phy@10209100 {
84 compatible = "mediatek,mt8173-hdmi-phy";
87 clock-names = "pll_ref";
88 clock-output-names = "hdmitx_dig_cts";
91 #clock-cells = <0>;
92 #phy-cells = <0>;