Lines Matching +full:calibration +full:- +full:data
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
23 - items:
24 - enum:
25 - mediatek,mt7623-mipi-tx
26 - const: mediatek,mt2701-mipi-tx
27 - items:
28 - enum:
29 - mediatek,mt8365-mipi-tx
30 - const: mediatek,mt8183-mipi-tx
31 - const: mediatek,mt2701-mipi-tx
32 - const: mediatek,mt8173-mipi-tx
33 - const: mediatek,mt8183-mipi-tx
40 - description: PLL reference clock
42 clock-output-names:
45 "#phy-cells":
48 "#clock-cells":
51 nvmem-cells:
53 description: A phandle to the calibration data provided by a nvmem device,
56 nvmem-cell-names:
58 - const: calibration-data
60 drive-strength-microamp:
68 - compatible
69 - reg
70 - clocks
71 - clock-output-names
72 - "#phy-cells"
73 - "#clock-cells"
78 - |
79 #include <dt-bindings/clock/mt8173-clk.h>
80 dsi-phy@10215000 {
81 compatible = "mediatek,mt8173-mipi-tx";
84 clock-output-names = "mipi_tx0_pll";
85 drive-strength-microamp = <4000>;
86 nvmem-cells= <&mipi_tx_calibration>;
87 nvmem-cell-names = "calibration-data";
88 #clock-cells = <0>;
89 #phy-cells = <0>;