Lines Matching +full:imx8mq +full:- +full:reset

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Richard Zhu <hongxing.zhu@nxp.com>
13   "#phy-cells":
18       - fsl,imx8mm-pcie-phy
26   clock-names:
28       - const: ref
33   reset-names:
35       - const: pciephy
37   fsl,refclk-pad-mode:
43       Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
48   fsl,tx-deemph-gen1:
49     description: Gen1 De-emphasis value (optional).
53   fsl,tx-deemph-gen2:
54     description: Gen2 De-emphasis value (optional).
58   fsl,clkreq-unsupported:
64   - "#phy-cells"
65   - compatible
66   - reg
67   - clocks
68   - clock-names
69   - fsl,refclk-pad-mode
74   - |
75     #include <dt-bindings/clock/imx8mm-clock.h>
76     #include <dt-bindings/phy/phy-imx8-pcie.h>
77     #include <dt-bindings/reset/imx8mq-reset.h>
79     pcie_phy: pcie-phy@32f00000 {
80             compatible = "fsl,imx8mm-pcie-phy";
83             clock-names = "ref";
84             assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
85             assigned-clock-rates = <100000000>;
86             assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
88             reset-names = "pciephy";
89             fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
90             #phy-cells = <0>;