Lines Matching +full:msi +full:- +full:controller

4 - compatible: Should contain "xlnx,nwl-pcie-2.11"
5 - #address-cells: Address representation for root ports, set to <3>
6 - #size-cells: Size representation for root ports, set to <2>
7 - #interrupt-cells: specifies the number of cells needed to encode an
9 - reg: Should contain Bridge, PCIe Controller registers location,
11 - reg-names: Must include the following entries:
13 	"pcireg": PCIe controller registers
15 - device_type: must be "pci"
16 - interrupts: Should contain NWL PCIe interrupt
17 - interrupt-names: Must include the following entries:
18 	"msi1, msi0": interrupt asserted when an MSI is received
21 - interrupt-map-mask and interrupt-map: standard PCI properties to define the
23 - ranges: ranges for the PCI memory regions (I/O space region is not
27 - msi-controller: indicates that this is MSI controller node
28 - msi-parent:  MSI parent of the root complex itself
29 - legacy-interrupt-controller: Interrupt controller device node for Legacy
31 	- interrupt-controller: identifies the node as an interrupt controller
32 	- #interrupt-cells: should be set to 1
33 	- #address-cells: specifies the number of cells needed to encode an
37 - dma-coherent: present if DMA operations are coherent
38 - clocks: Input clock specifier. Refer to common clock bindings
44 	#address-cells = <3>;
45 	#size-cells = <2>;
46 	compatible = "xlnx,nwl-pcie-2.11";
47 	#interrupt-cells = <1>;
48 	msi-controller;
50 	interrupt-parent = <&gic>;
52 	interrupt-names = "msi0", "msi1", "intx", "dummy", "misc";
53 	interrupt-map-mask = <0x0 0x0 0x0 0x7>;
54 	interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
59 	msi-parent = <&nwl_pcie>;
63 	reg-names = "breg", "pcireg", "cfg";
64 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-pre…
67 	pcie_intc: legacy-interrupt-controller {
68 		interrupt-controller;
69 		#address-cells = <0>;
70 		#interrupt-cells = <1>;