Lines Matching +full:syscon +full:- +full:pcie +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-host.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI Host (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-host.yaml#"
19 - const: ti,j721e-pcie-host
20 - description: PCIe controller in AM64
22 - const: ti,am64-pcie-host
23 - const: ti,j721e-pcie-host
24 - description: PCIe controller in J7200
26 - const: ti,j7200-pcie-host
27 - const: ti,j721e-pcie-host
32 reg-names:
34 - const: intd_cfg
35 - const: user_cfg
36 - const: reg
37 - const: cfg
39 ti,syscon-pcie-ctrl:
40 $ref: /schemas/types.yaml#/definitions/phandle-array
42 - items:
43 - description: Phandle to the SYSCON entry
44 - description: pcie_ctrl register offset within SYSCON
45 description: Specifier for configuring PCIe mode and link speed.
47 power-domains:
54 clock-specifier to represent input to the PCIe for 1 item.
57 clock-names:
60 - const: fck
61 - const: pcie_refclk
63 dma-coherent: true
65 vendor-id:
68 device-id:
70 - items:
71 - const: 0xb00d
72 - items:
73 - const: 0xb00f
74 - items:
75 - const: 0xb010
77 msi-map: true
80 - compatible
81 - reg
82 - reg-names
83 - ti,syscon-pcie-ctrl
84 - max-link-speed
85 - num-lanes
86 - power-domains
87 - clocks
88 - clock-names
89 - vendor-id
90 - device-id
91 - msi-map
92 - dma-ranges
93 - ranges
94 - reset-gpios
95 - phys
96 - phy-names
101 - |
102 #include <dt-bindings/soc/ti,sci_pm_domain.h>
103 #include <dt-bindings/gpio/gpio.h>
106 #address-cells = <2>;
107 #size-cells = <2>;
109 pcie0_rc: pcie@2900000 {
110 compatible = "ti,j721e-pcie-host";
115 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
116 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
117 max-link-speed = <3>;
118 num-lanes = <2>;
119 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
121 clock-names = "fck";
123 #address-cells = <3>;
124 #size-cells = <2>;
125 bus-range = <0x0 0xf>;
126 vendor-id = <0x104c>;
127 device-id = <0xb00d>;
128 msi-map = <0x0 &gic_its 0x0 0x10000>;
129 dma-coherent;
130 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
132 phy-names = "pcie-phy";
135 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;