Lines Matching +full:syscon +full:- +full:pcie +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: TI J721E PCI EP (PCIe Wrapper)
11 - Kishon Vijay Abraham I <kishon@ti.com>
14 - $ref: "cdns-pcie-ep.yaml#"
19 - const: ti,j721e-pcie-ep
20 - description: PCIe EP controller in AM64
22 - const: ti,am64-pcie-ep
23 - const: ti,j721e-pcie-ep
24 - description: PCIe EP controller in J7200
26 - const: ti,j7200-pcie-ep
27 - const: ti,j721e-pcie-ep
32 reg-names:
34 - const: intd_cfg
35 - const: user_cfg
36 - const: reg
37 - const: mem
39 ti,syscon-pcie-ctrl:
40 $ref: /schemas/types.yaml#/definitions/phandle-array
42 - items:
43 - description: Phandle to the SYSCON entry
44 - description: pcie_ctrl register offset within SYSCON
45 description: Specifier for configuring PCIe mode and link speed.
47 power-domains:
52 description: clock-specifier to represent input to the PCIe
54 clock-names:
56 - const: fck
58 dma-coherent:
59 description: Indicates that the PCIe IP block can ensure the coherency
62 - compatible
63 - reg
64 - reg-names
65 - ti,syscon-pcie-ctrl
66 - max-link-speed
67 - num-lanes
68 - power-domains
69 - clocks
70 - clock-names
71 - max-functions
72 - phys
73 - phy-names
78 - |
79 #include <dt-bindings/soc/ti,sci_pm_domain.h>
82 #address-cells = <2>;
83 #size-cells = <2>;
85 pcie0_ep: pcie-ep@d000000 {
86 compatible = "ti,j721e-pcie-ep";
91 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
92 ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
93 max-link-speed = <3>;
94 num-lanes = <2>;
95 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
97 clock-names = "fck";
98 max-functions = /bits/ 8 <6>;
99 dma-coherent;
101 phy-names = "pcie-phy";