Lines Matching +full:dw +full:- +full:pcie +full:- +full:ep
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier PCIe endpoint controller
10 UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
11 PCI core. It shares common features with the PCIe DesignWare core and
13 Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
19 - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
24 - socionext,uniphier-pro5-pcie-ep
25 - socionext,uniphier-nx1-pcie-ep
31 reg-names:
33 - items:
34 - const: dbi
35 - const: dbi2
36 - const: link
37 - const: addr_space
38 - items:
39 - const: dbi
40 - const: dbi2
41 - const: link
42 - const: addr_space
43 - const: atu
49 clock-names:
51 - items: # for Pro5
52 - const: gio
53 - const: link
54 - const: link # for NX1
60 reset-names:
62 - items: # for Pro5
63 - const: gio
64 - const: link
65 - const: link # for NX1
67 num-ib-windows:
70 num-ob-windows:
73 num-lanes: true
78 phy-names:
79 const: pcie-phy
82 - compatible
83 - reg
84 - reg-names
85 - clocks
86 - clock-names
87 - resets
88 - reset-names
93 - |
94 pcie_ep: pcie-ep@66000000 {
95 compatible = "socionext,uniphier-pro5-pcie-ep";
96 reg-names = "dbi", "dbi2", "link", "addr_space";
99 clock-names = "gio", "link";
101 reset-names = "gio", "link";
103 num-ib-windows = <16>;
104 num-ob-windows = <16>;
105 num-lanes = <4>;
106 phy-names = "pcie-phy";