Lines Matching +full:aux +full:- +full:bus
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
17 designware-pcie.txt.
20 - $ref: /schemas/pci/pci-bus.yaml#
25 - const: rockchip,rk3568-pcie
29 - description: Data Bus Interface (DBI) registers
30 - description: Rockchip designed configuration registers
31 - description: Config registers
33 reg-names:
35 - const: dbi
36 - const: apb
37 - const: config
41 - description: AHB clock for PCIe master
42 - description: AHB clock for PCIe slave
43 - description: AHB clock for PCIe dbi
44 - description: APB clock for PCIe
45 - description: Auxiliary clock for PCIe
47 clock-names:
49 - const: aclk_mst
50 - const: aclk_slv
51 - const: aclk_dbi
52 - const: pclk
53 - const: aux
55 msi-map: true
57 num-lanes: true
62 phy-names:
63 const: pcie-phy
65 power-domains:
74 reset-names:
77 vpcie3v3-supply: true
80 - compatible
81 - reg
82 - reg-names
83 - clocks
84 - clock-names
85 - msi-map
86 - num-lanes
87 - phys
88 - phy-names
89 - power-domains
90 - resets
91 - reset-names
96 - |
98 bus {
99 #address-cells = <2>;
100 #size-cells = <2>;
103 compatible = "rockchip,rk3568-pcie";
107 reg-names = "dbi", "apb", "config";
108 bus-range = <0x20 0x2f>;
112 clock-names = "aclk_mst", "aclk_slv",
114 "aux";
116 linux,pci-domain = <2>;
117 max-link-speed = <2>;
118 msi-map = <0x2000 &its 0x2000 0x1000>;
119 num-lanes = <2>;
121 phy-names = "pcie-phy";
122 power-domains = <&power 15>;
126 reset-names = "pipe";
127 #address-cells = <3>;
128 #size-cells = <2>;