Lines Matching +full:bpmp +full:- +full:bus +full:- +full:id
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
16 inherits all the common properties defined in snps,dw-pcie.yaml. Some of
20 See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
26 - nvidia,tegra194-pcie
27 - nvidia,tegra234-pcie
31 - description: controller's application logic registers
32 - description: configuration registers
33 - description: iATU and DMA registers. This is where the iATU (internal
36 - description: aperture where the Root Port's own configuration
39 reg-names:
41 - const: appl
42 - const: config
43 - const: atu_dma
44 - const: dbi
48 - description: controller interrupt
49 - description: MSI interrupt
51 interrupt-names:
53 - const: intr
54 - const: msi
58 - description: module clock
60 clock-names:
62 - const: core
66 - description: APB bus interface reset
67 - description: module reset
69 reset-names:
71 - const: apb
72 - const: core
78 phy-names:
81 - const: p2u-0
82 - const: p2u-1
83 - const: p2u-2
84 - const: p2u-3
85 - const: p2u-4
86 - const: p2u-5
87 - const: p2u-6
88 - const: p2u-7
90 power-domains:
96 Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
97 Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
101 - description: memory read client
102 - description: memory write client
104 interconnect-names:
106 - const: dma-mem # read
107 - const: write
109 dma-coherent: true
111 nvidia,bpmp:
112 $ref: /schemas/types.yaml#/definitions/phandle-array
114 Must contain a pair of phandles to BPMP controller node followed by
115 controller ID. Following are the controller IDs for each controller:
141 - items:
142 - description: phandle to BPMP controller node
143 - description: PCIe controller ID
146 nvidia,update-fc-fixup:
157 a) speed is Gen-2 and MPS is 256B
158 b) speed is >= Gen-3 with any MPS
162 nvidia,aspm-cmrt-us:
166 nvidia,aspm-pwr-on-t-us:
170 nvidia,aspm-l0s-entrance-latency-us:
173 vddio-pex-ctl-supply:
176 vpcie3v3-supply:
179 in p2972-0000 platform.
181 vpcie12v-supply:
184 in p2972-0000 platform.
186 nvidia,enable-srns:
190 Spread-Spectrum Clocking). NOTE: This is applicable only for
195 nvidia,enable-ext-refclk:
204 - $ref: /schemas/pci/snps,dw-pcie.yaml#
209 - interrupts
210 - interrupt-names
211 - interrupt-map
212 - interrupt-map-mask
213 - clocks
214 - clock-names
215 - resets
216 - reset-names
217 - power-domains
218 - vddio-pex-ctl-supply
219 - num-lanes
220 - phys
221 - phy-names
222 - nvidia,bpmp
225 - |
226 #include <dt-bindings/clock/tegra194-clock.h>
227 #include <dt-bindings/interrupt-controller/arm-gic.h>
228 #include <dt-bindings/power/tegra194-powergate.h>
229 #include <dt-bindings/reset/tegra194-reset.h>
231 bus@0 {
232 #address-cells = <2>;
233 #size-cells = <2>;
237 compatible = "nvidia,tegra194-pcie";
238 power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
243 reg-names = "appl", "config", "atu_dma", "dbi";
245 #address-cells = <3>;
246 #size-cells = <2>;
248 num-lanes = <8>;
249 linux,pci-domain = <0>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
254 clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
255 clock-names = "core";
257 resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
258 <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
259 reset-names = "apb", "core";
263 interrupt-names = "intr", "msi";
265 #interrupt-cells = <1>;
266 interrupt-map-mask = <0 0 0 0>;
267 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
269 nvidia,bpmp = <&bpmp 0>;
271 supports-clkreq;
272 nvidia,aspm-cmrt-us = <60>;
273 nvidia,aspm-pwr-on-t-us = <20>;
274 nvidia,aspm-l0s-entrance-latency-us = <3>;
276 bus-range = <0x0 0xff>;
278 … <0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
281 vddio-pex-ctl-supply = <&vdd_1v8ao>;
282 vpcie3v3-supply = <&vdd_3v3_pcie>;
283 vpcie12v-supply = <&vdd_12v_pcie>;
287 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
291 - |
292 #include <dt-bindings/clock/tegra234-clock.h>
293 #include <dt-bindings/interrupt-controller/arm-gic.h>
294 #include <dt-bindings/power/tegra234-powergate.h>
295 #include <dt-bindings/reset/tegra234-reset.h>
297 bus@0 {
298 #address-cells = <2>;
299 #size-cells = <2>;
303 compatible = "nvidia,tegra234-pcie";
304 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
309 reg-names = "appl", "config", "atu_dma", "dbi";
311 #address-cells = <3>;
312 #size-cells = <2>;
314 num-lanes = <4>;
315 num-viewport = <8>;
316 linux,pci-domain = <4>;
318 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
319 clock-names = "core";
321 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
322 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
323 reset-names = "apb", "core";
327 interrupt-names = "intr", "msi";
329 #interrupt-cells = <1>;
330 interrupt-map-mask = <0 0 0 0>;
331 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
333 nvidia,bpmp = <&bpmp 4>;
335 nvidia,aspm-cmrt-us = <60>;
336 nvidia,aspm-pwr-on-t-us = <20>;
337 nvidia,aspm-l0s-entrance-latency-us = <3>;
339 bus-range = <0x0 0xff>;
341 … <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
344 vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
348 phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";