Lines Matching +full:msi +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip PCIe Root Port Bridge Controller
10 - Daire McNamara <daire.mcnamara@microchip.com>
13 - $ref: /schemas/pci/pci-bus.yaml#
14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
18 const: microchip,pcie-host-1.0 # PolarFire
23 reg-names:
25 - const: cfg
26 - const: apb
40 - description: FIC0's clock
41 - description: FIC1's clock
42 - description: FIC2's clock
43 - description: FIC3's clock
45 clock-names:
49 0-3
53 pattern: '^fic[0-3]$'
58 - description: PCIe host controller
59 - description: builtin MSI controller
61 interrupt-names:
64 - const: pcie
65 - const: msi
70 dma-ranges:
74 msi-controller:
75 description: Identifies the node as an MSI controller.
77 msi-parent:
78 description: MSI controller the device is capable of using.
80 interrupt-controller:
83 '#address-cells':
86 '#interrupt-cells':
89 interrupt-controller: true
92 - '#address-cells'
93 - '#interrupt-cells'
94 - interrupt-controller
99 - reg
100 - reg-names
101 - "#interrupt-cells"
102 - interrupts
103 - interrupt-map-mask
104 - interrupt-map
105 - msi-controller
110 - |
112 #address-cells = <2>;
113 #size-cells = <2>;
115 compatible = "microchip,pcie-host-1.0";
118 reg-names = "cfg", "apb";
120 #address-cells = <3>;
121 #size-cells = <2>;
122 #interrupt-cells = <1>;
124 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
125 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
129 interrupt-parent = <&plic0>;
130 msi-parent = <&pcie0>;
131 msi-controller;
132 bus-range = <0x00 0x7f>;
134 pcie_intc0: interrupt-controller {
135 #address-cells = <0>;
136 #interrupt-cells = <1>;
137 interrupt-controller;