Lines Matching +full:msi +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
24 port->irq
26 +-+-+-+-+-+-+-+-+
28 +-+-+-+-+-+-+-+-+
31 +-------+ +------+ +-----------+
33 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
34 |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets)
35 +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+
37 | | | | | | | | | | | | (MSI vectors)
40 (MSI SET0) (MSI SET1) ... (MSI SET7)
42 With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43 each set has its own address for MSI message, and supports 32 MSI vectors
47 - $ref: /schemas/pci/pci-bus.yaml#
52 - items:
53 - enum:
54 - mediatek,mt8188-pcie
55 - mediatek,mt8195-pcie
56 - const: mediatek,mt8192-pcie
57 - const: mediatek,mt8192-pcie
62 reg-names:
64 - const: pcie-mac
77 reset-names:
80 - const: phy
81 - const: mac
86 clock-names:
88 - const: pl_250m
89 - const: tl_26m
90 - const: tl_96m
91 - const: tl_32k
92 - const: peri_26m
93 - enum:
94 - top_133m # for MT8192
95 - peri_mem # for MT8188/MT8195
97 assigned-clocks:
100 assigned-clock-parents:
106 phy-names:
108 - const: pcie-phy
110 '#interrupt-cells':
113 interrupt-controller:
114 description: Interrupt controller node for handling legacy PCI interrupts.
117 '#address-cells':
119 '#interrupt-cells':
121 interrupt-controller: true
124 - '#address-cells'
125 - '#interrupt-cells'
126 - interrupt-controller
131 - compatible
132 - reg
133 - reg-names
134 - interrupts
135 - ranges
136 - clocks
137 - clock-names
138 - '#interrupt-cells'
139 - interrupt-controller
144 - |
145 #include <dt-bindings/interrupt-controller/arm-gic.h>
146 #include <dt-bindings/interrupt-controller/irq.h>
149 #address-cells = <2>;
150 #size-cells = <2>;
153 compatible = "mediatek,mt8192-pcie";
155 #address-cells = <3>;
156 #size-cells = <2>;
158 reg-names = "pcie-mac";
160 bus-range = <0x00 0xff>;
169 clock-names = "pl_250m", "tl_26m", "tl_96m",
171 assigned-clocks = <&topckgen 50>;
172 assigned-clock-parents = <&topckgen 91>;
175 phy-names = "pcie-phy";
179 reset-names = "phy", "mac";
181 #interrupt-cells = <1>;
182 interrupt-map-mask = <0 0 0 0x7>;
183 interrupt-map = <0 0 0 1 &pcie_intc 0>,
187 pcie_intc: interrupt-controller {
188 #address-cells = <0>;
189 #interrupt-cells = <1>;
190 interrupt-controller;