Lines Matching +full:0 +full:x1e140000

26       - description: pcie port 0 RC control registers
34   'pcie@[0-2],0':
49         pattern: '^pcie-phy[0-2]$'
81         reg = <0x1e140000 0x100>,
82               <0x1e142000 0x100>,
83               <0x1e143000 0x100>,
84               <0x1e144000 0x100>;
89         pinctrl-0 = <&pcie_pins>;
91         ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>,  /* pci memory */
92                  <0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>;  /* io space */
94         interrupt-map-mask = <0xF800 0 0 0>;
95         interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
96                         <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
97                         <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
100         pcie@0,0 {
101             reg = <0x0000 0 0 0 0>;
106             interrupt-map-mask = <0 0 0 0>;
107             interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
115         pcie@1,0 {
116             reg = <0x0800 0 0 0 0>;
121             interrupt-map-mask = <0 0 0 0>;
122             interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
130         pcie@2,0 {
131             reg = <0x1000 0 0 0 0>;
136             interrupt-map-mask = <0 0 0 0>;
137             interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
140             phys = <&pcie2_phy 0>;