Lines Matching +full:designware +full:- +full:pcie

1 HiSilicon STB PCIe host bridge DT description
3 The HiSilicon STB PCIe host controller is based on the DesignWare PCIe core.
4 It shares common functions with the DesignWare PCIe core driver and inherits
6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible: Should be one of the following strings:
12 		"hisilicon,hi3798cv200-pcie"
13 - reg: Should contain sysctl, rc_dbi, config registers location and length.
14 - reg-names: Must include the following entries:
15   "control": control registers of PCIe controller;
16   "rc-dbi": configuration space of PCIe controller;
17   "config": configuration transaction space of PCIe controller.
18 - bus-range: PCI bus numbers covered.
19 - interrupts: MSI interrupt.
20 - interrupt-names: Must include "msi" entries.
21 - clocks: List of phandle and clock specifier pairs as listed in clock-names
23 - clock-name: Must include the following entries:
28 - resets: List of phandle and reset specifier pairs as listed in reset-names
30 - reset-names: Must include the following entries:
36 - reset-gpios: The gpio to generate PCIe PERST# assert and deassert signal.
37 - vpcie-supply: The regulator in charge of PCIe port power.
38 - phys: List of phandle and phy mode specifier, should be 0.
39 - phy-names: Must be "phy".
42 	pcie@f9860000 {
43 		compatible = "hisilicon,hi3798cv200-pcie";
47 		reg-names = "control", "rc-dbi", "config";
48 		#address-cells = <3>;
49 		#size-cells = <2>;
51 		bus-range = <0 15>;
52 		num-lanes = <1>;
56 		interrupt-names = "msi";
57 		#interrupt-cells = <1>;
58 		interrupt-map-mask = <0 0 0 0>;
59 		interrupt-map = <0 0 0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
64 		clock-names = "aux", "pipe", "sys", "bus";
66 		reset-names = "soft", "sys", "bus";
68 		phy-names = "phy";