Lines Matching +full:imx8mq +full:- +full:reset
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
15 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
18 - $ref: /schemas/pci/snps,dw-pcie.yaml#
23 - fsl,imx6q-pcie
24 - fsl,imx6sx-pcie
25 - fsl,imx6qp-pcie
26 - fsl,imx7d-pcie
27 - fsl,imx8mq-pcie
28 - fsl,imx8mm-pcie
29 - fsl,imx8mp-pcie
33 - description: Data Bus Interface (DBI) registers.
34 - description: PCIe configuration space region.
36 reg-names:
38 - const: dbi
39 - const: config
43 - description: builtin MSI controller.
45 interrupt-names:
47 - const: msi
52 - description: PCIe bridge clock.
53 - description: PCIe bus clock.
54 - description: PCIe PHY clock.
55 - description: Additional required clock entry for imx6sx-pcie,
56 imx8mq-pcie.
58 clock-names:
61 - const: pcie
62 - const: pcie_bus
63 - const: pcie_phy
64 - const: pcie_inbound_axi for imx6sx-pcie, pcie_aux for imx8mq-pcie
66 num-lanes:
69 fsl,imx7d-pcie-phy:
71 description: A phandle to an fsl,imx7d-pcie-phy node. Additional
72 required properties for imx7d-pcie and imx8mq-pcie.
74 power-domains:
76 - description: The phandle pointing to the DISPLAY domain for
77 imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
78 imx8mq-pcie.
79 - description: The phandle pointing to the PCIE_PHY power domains
80 for imx6sx-pcie.
82 power-domain-names:
84 - const: pcie
85 - const: pcie_phy
89 description: Phandles to PCIe-related reset lines exposed by SRC
90 IP block. Additional required by imx7d-pcie and imx8mq-pcie.
92 reset-names:
94 - const: pciephy
95 - const: apps
96 - const: turnoff
98 fsl,tx-deemph-gen1:
99 description: Gen1 De-emphasis value (optional required).
103 fsl,tx-deemph-gen2-3p5db:
104 description: Gen2 (3.5db) De-emphasis value (optional required).
108 fsl,tx-deemph-gen2-6db:
109 description: Gen2 (6db) De-emphasis value (optional required).
113 fsl,tx-swing-full:
118 fsl,tx-swing-low:
123 fsl,max-link-speed:
135 phy-names:
136 const: pcie-phy
138 reset-gpio:
140 reset signal. It's not polarity aware and defaults to active-low reset
141 sequence (L=reset state, H=operation state) (optional required).
143 reset-gpio-active-high:
144 description: If present then the reset sequence using the GPIO
145 specified in the "reset-gpio" property is reversed (H=reset state,
149 vpcie-supply:
155 vph-supply:
161 - compatible
162 - reg
163 - reg-names
164 - "#address-cells"
165 - "#size-cells"
166 - device_type
167 - bus-range
168 - ranges
169 - num-lanes
170 - interrupts
171 - interrupt-names
172 - "#interrupt-cells"
173 - interrupt-map-mask
174 - interrupt-map
175 - clocks
176 - clock-names
181 - |
182 #include <dt-bindings/clock/imx6qdl-clock.h>
183 #include <dt-bindings/interrupt-controller/arm-gic.h>
186 compatible = "fsl,imx6q-pcie";
189 reg-names = "dbi", "config";
190 #address-cells = <3>;
191 #size-cells = <2>;
193 bus-range = <0x00 0xff>;
196 num-lanes = <1>;
198 interrupt-names = "msi";
199 #interrupt-cells = <1>;
200 interrupt-map-mask = <0 0 0 0x7>;
201 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
208 clock-names = "pcie", "pcie_bus", "pcie_phy";