Lines Matching +full:dw +full:- +full:apb +full:- +full:gpio +full:- +full:port
6 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
11 - compatible:
13 - "amlogic,axg-pcie" for AXG SoC Family
14 - "amlogic,g12a-pcie" for G12A SoC Family
16 - reg:
18 - reg-names: Must be
19 - "elbi" External local bus interface registers
20 - "cfg" Meson specific registers
21 - "config" PCIe configuration space
22 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
23 - clocks: Must contain an entry for each entry in clock-names.
24 - clock-names: Must include the following entries:
25 - "pclk" PCIe GEN 100M PLL clock
26 - "port" PCIe_x(A or B) RC clock gate
27 - "general" PCIe Phy clock
28 - resets: phandle to the reset lines.
29 - reset-names: must contain "port" and "apb"
30 - "port" Port A or B reset
31 - "apb" Share APB reset
32 - phys: should contain a phandle to the PCIE phy
33 - phy-names: must contain "pcie"
35 - device_type:
36 should be "pci". As specified in snps,dw-pcie.yaml
42 compatible = "amlogic,axg-pcie", "snps,dw-pcie";
46 reg-names = "elbi", "cfg", "config";
47 reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
49 #interrupt-cells = <1>;
50 interrupt-map-mask = <0 0 0 0>;
51 interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
52 bus-range = <0x0 0xff>;
53 #address-cells = <3>;
54 #size-cells = <2>;
61 clock-names = "general",
63 "port";
66 reset-names = "port",
67 "apb";
69 phy-names = "pcie";