Lines Matching +full:auto +full:- +full:range
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,k3-am654-cpsw-nuss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grygorii Strashko <grygorii.strashko@ti.com>
11 - Sekhar Nori <nsekhar@ti.com>
22 Complex (UDMA-P) controller.
35 VLAN support, 802.1Q compliant, Auto add port VLAN for untagged frames on
36 ingress, Auto VLAN removal on egress and auto pad to minimum frame size.
52 "#address-cells": true
53 "#size-cells": true
57 - ti,am654-cpsw-nuss
58 - ti,j7200-cpswxg-nuss
59 - ti,j721e-cpsw-nuss
60 - ti,am642-cpsw-nuss
65 The physical base address and size of full the CPSWxG NUSS IO range
67 reg-names:
69 - const: cpsw_nuss
73 dma-coherent: true
79 clock-names:
81 - const: fck
83 assigned-clock-parents: true
85 assigned-clocks: true
87 power-domains:
93 dma-names:
95 - const: tx0
96 - const: tx1
97 - const: tx2
98 - const: tx3
99 - const: tx4
100 - const: tx5
101 - const: tx6
102 - const: tx7
103 - const: rx
105 ethernet-ports:
108 '#address-cells':
110 '#size-cells':
114 "^port@[1-4]$":
118 $ref: ethernet-controller.yaml#
129 description: phandle on phy-gmii-sel PHY
134 ti,mac-only:
137 Specifies the port works in mac-only mode.
139 ti,syscon-efuse:
140 $ref: /schemas/types.yaml#/definitions/phandle-array
142 - items:
143 - description: Phandle to the system control device node which
145 - description: offset to efuse registers???
148 to efuse IO range with MAC addresses
151 - reg
152 - phys
157 "^mdio@[0-9a-f]+$":
159 $ref: "ti,davinci-mdio.yaml#"
164 "^cpts@[0-9a-f]+":
166 $ref: "ti,k3-am654-cpts.yaml#"
171 - compatible
172 - reg
173 - reg-names
174 - ranges
175 - clocks
176 - clock-names
177 - power-domains
178 - dmas
179 - dma-names
180 - '#address-cells'
181 - '#size-cells'
184 - if:
189 const: ti,j7200-cpswxg-nuss
192 ethernet-ports:
194 "^port@[3-4]$": false
199 - |
200 #include <dt-bindings/pinctrl/k3.h>
201 #include <dt-bindings/soc/ti,sci_pm_domain.h>
202 #include <dt-bindings/net/ti-dp83867.h>
203 #include <dt-bindings/interrupt-controller/irq.h>
204 #include <dt-bindings/interrupt-controller/arm-gic.h>
207 #address-cells = <2>;
208 #size-cells = <2>;
211 compatible = "ti,am654-cpsw-nuss";
212 #address-cells = <2>;
213 #size-cells = <2>;
215 reg-names = "cpsw_nuss";
217 dma-coherent;
219 clock-names = "fck";
220 power-domains = <&k3_pds 5 TI_SCI_PD_EXCLUSIVE>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
233 dma-names = "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
236 ethernet-ports {
237 #address-cells = <1>;
238 #size-cells = <0>;
242 ti,mac-only;
244 ti,syscon-efuse = <&mcu_conf 0x200>;
247 phy-mode = "rgmii-rxid";
248 phy-handle = <&phy0>;
253 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
255 #address-cells = <1>;
256 #size-cells = <0>;
258 clock-names = "fck";
261 phy0: ethernet-phy@0 {
263 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
264 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
270 compatible = "ti,am65-cpts";
273 clock-names = "cpts";
274 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "cpts";
276 ti,cpts-ext-ts-inputs = <4>;
277 ti,cpts-periodic-outputs = <2>;