Lines Matching +full:mod +full:- +full:def0 +full:- +full:gpios

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Small Form Factor (SFF) Committee Small Form-factor Pluggable (SFP)
11   - Russell King <linux@armlinux.org.uk>
16       - sff,sfp  # for SFP modules
17       - sff,sff  # for soldered down SFF modules
19   i2c-bus:
24   maximum-power-milliwatt:
28       allowable by a module in the slot, in milli-Watts. Presently, modules can
31   "mod-def0-gpios":
34       GPIO phandle and a specifier of the MOD-DEF0 (AKA Mod_ABS) module
38   "los-gpios":
44   "tx-fault-gpios":
50   "tx-disable-gpios":
56   "rate-select0-gpios":
60       output gpio signal, low - low Rx rate, high - high Rx rate Must not be
63   "rate-select1-gpios":
67       output gpio signal (SFP+ only), low - low Tx rate, high - high Tx rate. Must
71   - if:
78         mod-def0-gpios: false
79         rate-select0-gpios: false
80         rate-select1-gpios: false
83   - compatible
84   - i2c-bus
89   - | # Direct serdes to SFP connection
90     #include <dt-bindings/gpio/gpio.h>
94       i2c-bus = <&sfp_1g_i2c>;
95       los-gpios = <&cpm_gpio2 22 GPIO_ACTIVE_HIGH>;
96       mod-def0-gpios = <&cpm_gpio2 21 GPIO_ACTIVE_LOW>;
97       maximum-power-milliwatt = <1000>;
98       pinctrl-names = "default";
99       pinctrl-0 = <&cpm_sfp_1g_pins &cps_sfp_1g_pins>;
100       tx-disable-gpios = <&cps_gpio1 24 GPIO_ACTIVE_HIGH>;
101       tx-fault-gpios = <&cpm_gpio2 19 GPIO_ACTIVE_HIGH>;
105       phy-names = "comphy";
110   - | # Serdes to PHY to SFP connection
111     #include <dt-bindings/gpio/gpio.h>
112     #include <dt-bindings/interrupt-controller/arm-gic.h>
116       i2c-bus = <&sfp_i2c>;
117       los-gpios = <&cps_gpio1 28 GPIO_ACTIVE_HIGH>;
118       mod-def0-gpios = <&cps_gpio1 27 GPIO_ACTIVE_LOW>;
119       pinctrl-names = "default";
120       pinctrl-0 = <&cps_sfpp0_pins>;
121       tx-disable-gpios = <&cps_gpio1 29 GPIO_ACTIVE_HIGH>;
122       tx-fault-gpios  = <&cps_gpio1 26 GPIO_ACTIVE_HIGH>;
126       #address-cells = <1>;
127       #size-cells = <0>;
129       phy: ethernet-phy@0 {
130         compatible = "ethernet-phy-ieee802.3-c45";
131         pinctrl-names = "default";
132         pinctrl-0 = <&cpm_phy0_pins &cps_phy0_pins>;
141       phy-mode = "10gbase-kr";