Lines Matching +full:syscon +full:- +full:pcie +full:- +full:mode
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Bianconi <lorenzo@kernel.org>
11 - Felix Fietkau <nbd@nbd.name>
20 - mediatek,mt2701-eth
21 - mediatek,mt7623-eth
22 - mediatek,mt7622-eth
23 - mediatek,mt7629-eth
24 - mediatek,mt7986-eth
25 - ralink,rt5350-eth
31 clock-names: true
37 power-domains:
43 reset-names:
45 - const: fe
46 - const: gmac
47 - const: ppe
52 Phandle to the syscon node that handles the port setup.
54 cci-control-port: true
63 $ref: /schemas/types.yaml#/definitions/phandle-array
69 A list of phandle to the syscon node that handles the SGMII setup which is required for
73 $ref: /schemas/types.yaml#/definitions/phandle-array
81 dma-coherent: true
83 mdio-bus:
87 "#address-cells":
90 "#size-cells":
94 - $ref: "ethernet-controller.yaml#"
95 - if:
100 - mediatek,mt2701-eth
101 - mediatek,mt7623-eth
111 clock-names:
113 - const: ethif
114 - const: esw
115 - const: gp1
116 - const: gp2
121 Phandle to the syscon node that handles the ports slew rate and
126 - if:
130 const: mediatek,mt7622-eth
140 clock-names:
142 - const: ethif
143 - const: esw
144 - const: gp0
145 - const: gp1
146 - const: gp2
147 - const: sgmii_tx250m
148 - const: sgmii_rx250m
149 - const: sgmii_cdr_ref
150 - const: sgmii_cdr_fb
151 - const: sgmii_ck
152 - const: eth2pll
158 mediatek,pcie-mirror:
161 Phandle to the mediatek pcie-mirror controller.
163 - if:
167 const: mediatek,mt7629-eth
177 clock-names:
179 - const: ethif
180 - const: sgmiitop
181 - const: esw
182 - const: gp0
183 - const: gp1
184 - const: gp2
185 - const: fe
186 - const: sgmii_tx250m
187 - const: sgmii_rx250m
188 - const: sgmii_cdr_ref
189 - const: sgmii_cdr_fb
190 - const: sgmii2_tx250m
191 - const: sgmii2_rx250m
192 - const: sgmii2_cdr_ref
193 - const: sgmii2_cdr_fb
194 - const: sgmii_ck
195 - const: eth2pll
200 Phandle to the syscon node that handles the path from GMAC to
209 - if:
213 const: mediatek,mt7986-eth
223 clock-names:
225 - const: fe
226 - const: gp2
227 - const: gp1
228 - const: wocpu1
229 - const: wocpu0
230 - const: sgmii_tx250m
231 - const: sgmii_rx250m
232 - const: sgmii_cdr_ref
233 - const: sgmii_cdr_fb
234 - const: sgmii2_tx250m
235 - const: sgmii2_rx250m
236 - const: sgmii2_cdr_ref
237 - const: sgmii2_cdr_fb
238 - const: netsys0
239 - const: netsys1
245 mediatek,wed-pcie:
248 Phandle to the mediatek wed-pcie controller.
251 "^mac@[0-1]$":
255 - $ref: ethernet-controller.yaml#
260 const: mediatek,eth-mac
265 phy-handle: true
267 phy-mode: true
270 - reg
271 - compatible
272 - phy-handle
275 - compatible
276 - reg
277 - interrupts
278 - clocks
279 - clock-names
280 - mediatek,ethsys
285 - |
286 #include <dt-bindings/interrupt-controller/arm-gic.h>
287 #include <dt-bindings/interrupt-controller/irq.h>
288 #include <dt-bindings/clock/mt7622-clk.h>
289 #include <dt-bindings/power/mt7622-power.h>
292 #address-cells = <2>;
293 #size-cells = <2>;
296 compatible = "mediatek,mt7622-eth";
312 clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
316 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
319 cci-control-port = <&cci_control2>;
320 mediatek,pcie-mirror = <&pcie_mirror>;
322 dma-coherent;
324 #address-cells = <1>;
325 #size-cells = <0>;
327 mdio0: mdio-bus {
328 #address-cells = <1>;
329 #size-cells = <0>;
331 phy0: ethernet-phy@0 {
335 phy1: ethernet-phy@1 {
341 compatible = "mediatek,eth-mac";
342 phy-mode = "rgmii";
343 phy-handle = <&phy0>;
348 compatible = "mediatek,eth-mac";
349 phy-mode = "rgmii";
350 phy-handle = <&phy1>;
356 - |
357 #include <dt-bindings/interrupt-controller/arm-gic.h>
358 #include <dt-bindings/interrupt-controller/irq.h>
359 #include <dt-bindings/clock/mt7622-clk.h>
362 #address-cells = <2>;
363 #size-cells = <2>;
376 compatible = "mediatek,mt7986-eth";
397 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
405 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
407 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
410 #address-cells = <1>;
411 #size-cells = <0>;
413 mdio: mdio-bus {
414 #address-cells = <1>;
415 #size-cells = <0>;
417 phy5: ethernet-phy@0 {
418 compatible = "ethernet-phy-id67c9.de0a";
419 phy-mode = "2500base-x";
420 reset-gpios = <&pio 6 1>;
421 reset-deassert-us = <20000>;
425 phy6: ethernet-phy@1 {
426 compatible = "ethernet-phy-id67c9.de0a";
427 phy-mode = "2500base-x";
433 compatible = "mediatek,eth-mac";
434 phy-mode = "2500base-x";
435 phy-handle = <&phy5>;
440 compatible = "mediatek,eth-mac";
441 phy-mode = "2500base-x";
442 phy-handle = <&phy6>;