Lines Matching +full:rx +full:- +full:internal +full:- +full:delay
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
34 - const: ethernet-phy-ieee802.3-c45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
46 - items:
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c22
49 - items:
50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51 - const: ethernet-phy-ieee802.3-c45
62 max-speed:
64 - 10
65 - 100
66 - 1000
67 - 2500
68 - 5000
69 - 10000
70 - 20000
71 - 25000
72 - 40000
73 - 50000
74 - 56000
75 - 100000
76 - 200000
80 phy-10base-t1l-2.4vpp:
89 broken-turn-around:
96 enet-phy-lane-swap:
99 If set, indicates the PHY will swap the TX/RX lanes to
103 enet-phy-lane-no-swap:
107 TX/RX lanes. This property allows the PHY to work correcly after
111 eee-broken-100tx:
117 eee-broken-1000t:
123 eee-broken-10gt:
129 eee-broken-1000kx:
135 eee-broken-10gkx4:
141 eee-broken-10gkr:
148 $ref: /schemas/types.yaml#/definitions/phandle-array
153 phy-is-integrated:
165 reset-names:
168 reset-gpios:
173 reset-assert-us:
175 Delay after the reset was asserted in microseconds. If this
176 property is missing the delay will be skipped.
178 reset-deassert-us:
180 Delay after the reset was deasserted in microseconds. If
181 this property is missing the delay will be skipped.
188 rx-internal-delay-ps:
190 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
191 PHY's that have configurable RX internal delays. If this property is
192 present then the PHY applies the RX delay.
194 tx-internal-delay-ps:
196 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
197 PHY's that have configurable TX internal delays. If this property is
198 present then the PHY applies the TX delay.
201 - reg
206 - |
208 #address-cells = <1>;
209 #size-cells = <0>;
211 ethernet-phy@0 {
212 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
213 interrupt-parent = <&PIC>;
218 reset-names = "phy";
219 reset-gpios = <&gpio1 4 1>;
220 reset-assert-us = <1000>;
221 reset-deassert-us = <2000>;