Lines Matching +full:phy +full:- +full:10 +full:base +full:- +full:t1l +full:- +full:2
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ethernet PHY Generic Binding
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
28 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
32 - const: ethernet-phy-ieee802.3-c22
34 - const: ethernet-phy-ieee802.3-c45
36 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
38 If the PHY reports an incorrect ID (or none at all) then the
39 compatible list may contain an entry with the correct PHY ID
41 The first group of digits is the 16 bit Phy Identifier 1
43 second group of digits is the Phy Identifier 2 register,
44 this is the chip vendor OUI bits 19:24, followed by 10
46 - items:
47 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
48 - const: ethernet-phy-ieee802.3-c22
49 - items:
50 - pattern: "^ethernet-phy-id[a-f0-9]{4}\\.[a-f0-9]{4}$"
51 - const: ethernet-phy-ieee802.3-c45
57 The ID number for the PHY.
62 max-speed:
64 - 10
65 - 100
66 - 1000
67 - 2500
68 - 5000
69 - 10000
70 - 20000
71 - 25000
72 - 40000
73 - 50000
74 - 56000
75 - 100000
76 - 200000
78 Maximum PHY supported speed in Mbits / seconds.
80 phy-10base-t1l-2.4vpp:
89 broken-turn-around:
92 If set, indicates the PHY device does not correctly release
96 enet-phy-lane-swap:
99 If set, indicates the PHY will swap the TX/RX lanes to
103 enet-phy-lane-no-swap:
106 If set, indicates that PHY will disable swap of the
107 TX/RX lanes. This property allows the PHY to work correcly after
111 eee-broken-100tx:
117 eee-broken-1000t:
123 eee-broken-10gt:
129 eee-broken-1000kx:
135 eee-broken-10gkx4:
141 eee-broken-10gkr:
148 $ref: /schemas/types.yaml#/definitions/phandle-array
153 phy-is-integrated:
156 If set, indicates that the PHY is integrated into the same
158 should be configured to ensure the integrated PHY is
160 should be configured so that the external PHY is used.
165 reset-names:
166 const: phy
168 reset-gpios:
171 The GPIO phandle and specifier for the PHY reset signal.
173 reset-assert-us:
178 reset-deassert-us:
188 rx-internal-delay-ps:
190 RGMII Receive PHY Clock Delay defined in pico seconds. This is used for
191 PHY's that have configurable RX internal delays. If this property is
192 present then the PHY applies the RX delay.
194 tx-internal-delay-ps:
196 RGMII Transmit PHY Clock Delay defined in pico seconds. This is used for
197 PHY's that have configurable TX internal delays. If this property is
198 present then the PHY applies the TX delay.
201 - reg
206 - |
208 #address-cells = <1>;
209 #size-cells = <0>;
211 ethernet-phy@0 {
212 compatible = "ethernet-phy-id0141.0e90", "ethernet-phy-ieee802.3-c45";
213 interrupt-parent = <&PIC>;
218 reset-names = "phy";
219 reset-gpios = <&gpio1 4 1>;
220 reset-assert-us = <1000>;
221 reset-deassert-us = <2000>;