Lines Matching +full:mode +full:- +full:switch
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Atheros QCA83xx switch family
10 - John Crispin <john@phrozen.org>
13 If the QCA8K switch is connect to an SoC's external mdio-bus, each subnode
16 ID. To declare the internal mdio-bus configuration, declare an MDIO node in
17 the switch node and declare the phandle for the port, referencing the internal
18 PHY it is connected to. In this config, an internal mdio-bus is registered and
20 mdio-bus configurations are not supported by the hardware.
25 - enum:
26 - qca,qca8327
27 - qca,qca8328
28 - qca,qca8334
29 - qca,qca8337
31 qca,qca8328: referenced as AR8328(N)-AK1(A/B) QFN 176 pin package
32 qca,qca8327: referenced as AR8327(N)-AL1A DR-QFN 148 pin package
33 qca,qca8334: referenced as QCA8334-AL3C QFN 88 pin package
34 qca,qca8337: referenced as QCA8337N-AL3(B/C) DR-QFN 148 pin package
39 reset-gpios:
44 qca,ignore-power-on-sel:
47 Ignore power-on pin strapping to configure LED open-drain or EEPROM
51 qca,led-open-drain:
54 Set LEDs to open-drain mode. This requires the qca,ignore-power-on-sel to
56 OEM does not use pin strapping to set this mode and prefers to set it
57 using SW regs. The pin strappings related to LED open-drain mode are
63 description: Qca8k switch have an internal mdio to access switch port.
67 mdio is the switch reg with an offset of -1.
70 "^(ethernet-)?ports$":
73 '#address-cells':
75 '#size-cells':
79 "^(ethernet-)?port@[0-6]$":
81 description: Ethernet switch ports
83 $ref: dsa-port.yaml#
86 qca,sgmii-rxclk-falling-edge:
92 qca,sgmii-txclk-falling-edge:
97 qca,sgmii-enable-pll:
110 - required:
111 - ports
112 - required:
113 - ethernet-ports
116 - compatible
117 - reg
122 - |
123 #include <dt-bindings/gpio/gpio.h>
126 #address-cells = <1>;
127 #size-cells = <0>;
129 external_phy_port1: ethernet-phy@0 {
133 external_phy_port2: ethernet-phy@1 {
137 external_phy_port3: ethernet-phy@2 {
141 external_phy_port4: ethernet-phy@3 {
145 external_phy_port5: ethernet-phy@4 {
149 switch@10 {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
157 #address-cells = <1>;
158 #size-cells = <0>;
163 phy-mode = "rgmii";
165 fixed-link {
167 full-duplex;
174 phy-handle = <&external_phy_port1>;
180 phy-handle = <&external_phy_port2>;
186 phy-handle = <&external_phy_port3>;
192 phy-handle = <&external_phy_port4>;
198 phy-handle = <&external_phy_port5>;
203 - |
204 #include <dt-bindings/gpio/gpio.h>
207 #address-cells = <1>;
208 #size-cells = <0>;
210 switch@10 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
218 #address-cells = <1>;
219 #size-cells = <0>;
224 phy-mode = "rgmii";
226 fixed-link {
228 full-duplex;
235 phy-mode = "internal";
236 phy-handle = <&internal_phy_port1>;
242 phy-mode = "internal";
243 phy-handle = <&internal_phy_port2>;
249 phy-mode = "internal";
250 phy-handle = <&internal_phy_port3>;
256 phy-mode = "internal";
257 phy-handle = <&internal_phy_port4>;
263 phy-mode = "internal";
264 phy-handle = <&internal_phy_port5>;
270 phy-mode = "sgmii";
272 qca,sgmii-rxclk-falling-edge;
274 fixed-link {
276 full-duplex;
282 #address-cells = <1>;
283 #size-cells = <0>;
285 internal_phy_port1: ethernet-phy@0 {
289 internal_phy_port2: ethernet-phy@1 {
293 internal_phy_port3: ethernet-phy@2 {
297 internal_phy_port4: ethernet-phy@3 {
301 internal_phy_port5: ethernet-phy@4 {