Lines Matching +full:phy +full:- +full:reset +full:- +full:gpio
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
16 There are two versions of MT7530, standalone and in a multi-chip module.
18 MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN,
31 - Port 5 can be used as a CPU port.
33 - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC
37 The driver looks up the reg on the ethernet-phy node which the phy-handle
38 property refers to on the gmac node to mux the specified phy.
40 The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the
42 MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this.
45 - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave.
48 For multi-chip module MT7530:
50 - Port 5 can be used as a CPU port.
52 - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC.
56 The driver looks up the reg on the ethernet-phy node which the phy-handle
57 property refers to on the gmac node to mux the specified phy.
62 - In case of an external phy wired to gmac1 of the SoC, port 5 must not be
65 In case of muxing PHY 0 or 4, the external phy must not be enabled.
70 - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave.
71 The external phy must be wired TX to TX to gmac1 of the SoC for this to
74 Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX.
76 For the MT7621 SoCs, rgmii2 group must be claimed with gpio function.
82 - description:
83 Standalone MT7530 and multi-chip module MT7530 in MT7623AI SoC
86 - description:
90 - description:
91 Multi-chip module MT7530 in MT7621AT, MT7621DAT and MT7621ST SoCs
97 core-supply:
101 "#gpio-cells":
104 gpio-controller:
107 If defined, LED controller of the MT7530 switch will run on GPIO mode.
110 port 0 LED 0..2 as GPIO 0..2
111 port 1 LED 0..2 as GPIO 3..5
112 port 2 LED 0..2 as GPIO 6..8
113 port 3 LED 0..2 as GPIO 9..11
114 port 4 LED 0..2 as GPIO 12..14
116 "#interrupt-cells":
119 interrupt-controller: true
124 io-supply:
127 See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt for
134 switch is a part of the multi-chip module.
136 reset-gpios:
138 GPIO to reset the switch. Use this if mediatek,mcm is not used.
139 This property is optional because some boards share the reset line with
141 reset line is used.
144 reset-names:
149 Phandle pointing to the system reset controller with line index for the
154 "^(ethernet-)?ports$":
158 "^(ethernet-)?port@[0-9]+$":
171 - $ref: dsa-port.yaml#
172 - if:
178 - 5
179 - 6
182 - compatible
183 - reg
186 mt7530-dsa-port:
188 "^(ethernet-)?ports$":
190 "^(ethernet-)?port@[0-9]+$":
200 phy-mode:
202 - gmii
203 - mii
204 - rgmii
207 phy-mode:
209 - rgmii
210 - trgmii
212 mt7531-dsa-port:
214 "^(ethernet-)?ports$":
216 "^(ethernet-)?port@[0-9]+$":
226 phy-mode:
228 - 1000base-x
229 - 2500base-x
230 - rgmii
231 - sgmii
234 phy-mode:
236 - 1000base-x
237 - 2500base-x
238 - sgmii
241 - $ref: dsa.yaml#
242 - if:
244 - mediatek,mcm
247 reset-gpios: false
250 - resets
251 - reset-names
253 - dependencies:
254 interrupt-controller: [ interrupts ]
256 - if:
261 $ref: "#/$defs/mt7530-dsa-port"
263 - core-supply
264 - io-supply
266 - if:
271 $ref: "#/$defs/mt7531-dsa-port"
273 gpio-controller: false
276 - if:
281 $ref: "#/$defs/mt7530-dsa-port"
283 - mediatek,mcm
289 - |
290 #include <dt-bindings/gpio/gpio.h>
293 #address-cells = <1>;
294 #size-cells = <0>;
300 reset-gpios = <&pio 33 0>;
302 core-supply = <&mt6323_vpa_reg>;
303 io-supply = <&mt6323_vemc3v3_reg>;
305 ethernet-ports {
306 #address-cells = <1>;
307 #size-cells = <0>;
337 phy-mode = "rgmii";
339 fixed-link {
341 full-duplex;
350 - |
351 #include <dt-bindings/reset/mt2701-resets.h>
354 #address-cells = <1>;
355 #size-cells = <0>;
363 reset-names = "mcm";
365 core-supply = <&mt6323_vpa_reg>;
366 io-supply = <&mt6323_vemc3v3_reg>;
368 ethernet-ports {
369 #address-cells = <1>;
370 #size-cells = <0>;
400 phy-mode = "trgmii";
402 fixed-link {
404 full-duplex;
413 - |
414 #include <dt-bindings/gpio/gpio.h>
415 #include <dt-bindings/interrupt-controller/irq.h>
418 #address-cells = <1>;
419 #size-cells = <0>;
425 reset-gpios = <&pio 54 0>;
427 interrupt-controller;
428 #interrupt-cells = <1>;
429 interrupt-parent = <&pio>;
432 ethernet-ports {
433 #address-cells = <1>;
434 #size-cells = <0>;
464 phy-mode = "2500base-x";
466 fixed-link {
468 full-duplex;
477 - |
478 #include <dt-bindings/interrupt-controller/mips-gic.h>
479 #include <dt-bindings/reset/mt7621-reset.h>
482 #address-cells = <1>;
483 #size-cells = <0>;
491 reset-names = "mcm";
493 interrupt-controller;
494 #interrupt-cells = <1>;
495 interrupt-parent = <&gic>;
498 ethernet-ports {
499 #address-cells = <1>;
500 #size-cells = <0>;
530 phy-mode = "trgmii";
532 fixed-link {
534 full-duplex;
543 - |
544 #include <dt-bindings/interrupt-controller/mips-gic.h>
545 #include <dt-bindings/reset/mt7621-reset.h>
548 #address-cells = <1>;
549 #size-cells = <0>;
551 pinctrl-names = "default";
552 pinctrl-0 = <&rgmii2_pins>;
555 compatible = "mediatek,eth-mac";
558 phy-mode = "rgmii";
559 phy-handle = <&example5_ethphy4>;
563 #address-cells = <1>;
564 #size-cells = <0>;
567 example5_ethphy4: ethernet-phy@4 {
577 reset-names = "mcm";
579 interrupt-controller;
580 #interrupt-cells = <1>;
581 interrupt-parent = <&gic>;
584 ethernet-ports {
585 #address-cells = <1>;
586 #size-cells = <0>;
618 phy-mode = "trgmii";
620 fixed-link {
622 full-duplex;
631 # Example 6: MT7621: mux external phy to SoC's gmac1
632 - |
633 #include <dt-bindings/interrupt-controller/mips-gic.h>
634 #include <dt-bindings/reset/mt7621-reset.h>
637 #address-cells = <1>;
638 #size-cells = <0>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&rgmii2_pins>;
644 compatible = "mediatek,eth-mac";
647 phy-mode = "rgmii";
648 phy-handle = <&example6_ethphy7>;
652 #address-cells = <1>;
653 #size-cells = <0>;
655 /* External PHY */
656 example6_ethphy7: ethernet-phy@7 {
658 phy-mode = "rgmii";
667 reset-names = "mcm";
669 interrupt-controller;
670 #interrupt-cells = <1>;
671 interrupt-parent = <&gic>;
674 ethernet-ports {
675 #address-cells = <1>;
676 #size-cells = <0>;
706 phy-mode = "trgmii";
708 fixed-link {
710 full-duplex;
719 # Example 7: MT7621: mux external phy to MT7530's port 5
720 - |
721 #include <dt-bindings/interrupt-controller/mips-gic.h>
722 #include <dt-bindings/reset/mt7621-reset.h>
725 #address-cells = <1>;
726 #size-cells = <0>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&rgmii2_pins>;
732 #address-cells = <1>;
733 #size-cells = <0>;
735 /* External PHY */
736 example7_ethphy7: ethernet-phy@7 {
738 phy-mode = "rgmii";
747 reset-names = "mcm";
749 interrupt-controller;
750 #interrupt-cells = <1>;
751 interrupt-parent = <&gic>;
754 ethernet-ports {
755 #address-cells = <1>;
756 #size-cells = <0>;
786 phy-mode = "rgmii-txid";
787 phy-handle = <&example7_ethphy7>;
793 phy-mode = "trgmii";
795 fixed-link {
797 full-duplex;