Lines Matching +full:ecc +full:- +full:engine
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 The ECC strength and ECC step size properties define the user
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
31 pattern: "^nand-controller(@.*)?"
33 "#address-cells":
36 "#size-cells":
41 cs-gpios:
43 Array of chip-select available to the controller. The first
44 entries are a 1:1 mapping of the available chip-select on the
46 chip-select as needed may follow and should be phandles of GPIO
53 "^nand@[a-f0-9]$":
55 $ref: "nand-chip.yaml#"
60 Contains the chip-select IDs.
62 nand-ecc-placement:
64 Location of the ECC bytes. This location is unknown by default
65 but can be explicitly set to "oob", if all ECC bytes are
66 known to be stored in the OOB area, or "interleaved" if ECC
71 nand-bus-width:
78 nand-on-flash-bbt:
83 it as the device ages. Otherwise, the out-of-band area of a
89 nand-ecc-maximize:
91 Whether or not the ECC strength should be maximized. The
92 maximum ECC strength is both controller and chip
93 dependent. The ECC engine has to select the ECC config
96 only the in-band area is used by the upper layers, and you
100 nand-is-boot-medium:
103 use this information to select ECC algorithms supported by
107 nand-rb:
110 $ref: /schemas/types.yaml#/definitions/uint32-array
112 rb-gpios:
119 wp-gpios:
127 - reg
130 - "#address-cells"
131 - "#size-cells"
136 - |
137 nand-controller {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */