Lines Matching +full:ecc +full:- +full:engine
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
14 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
15 flash chips. It has a memory-mapped register interface for both control
17 is paired with a custom DMA engine (inventively named "Flash DMA") which
25 -- Additional SoC-specific NAND controller properties --
33 interesting ways, sometimes with registers that lump multiple NAND-related
42 - items:
43 - enum:
44 - brcm,brcmnand-v2.1
45 - brcm,brcmnand-v2.2
46 - brcm,brcmnand-v4.0
47 - brcm,brcmnand-v5.0
48 - brcm,brcmnand-v6.0
49 - brcm,brcmnand-v6.1
50 - brcm,brcmnand-v6.2
51 - brcm,brcmnand-v7.0
52 - brcm,brcmnand-v7.1
53 - brcm,brcmnand-v7.2
54 - brcm,brcmnand-v7.3
55 - const: brcm,brcmnand
56 - description: BCM63138 SoC-specific NAND controller
58 - const: brcm,nand-bcm63138
59 - enum:
60 - brcm,brcmnand-v7.0
61 - brcm,brcmnand-v7.1
62 - const: brcm,brcmnand
63 - description: iProc SoC-specific NAND controller
65 - const: brcm,nand-iproc
66 - const: brcm,brcmnand-v6.1
67 - const: brcm,brcmnand
68 - description: BCM63168 SoC-specific NAND controller
70 - const: brcm,nand-bcm63168
71 - const: brcm,nand-bcm6368
72 - const: brcm,brcmnand-v4.0
73 - const: brcm,brcmnand
79 reg-names:
83 enum: [ nand, flash-dma, flash-edu, nand-cache, nand-int-base, iproc-idm, iproc-ext ]
88 - description: NAND CTLRDY interrupt
89 - description: FLASH_DMA_DONE if flash DMA is available
90 - description: FLASH_EDU_DONE if EDU is available
92 interrupt-names:
95 - const: nand_ctlrdy
96 - const: flash_dma_done
97 - const: flash_edu_done
103 clock-names:
106 brcm,nand-has-wp:
108 Some versions of this IP include a write-protect
115 "^nand@[a-f0-9]$":
121 nand-ecc-step-size:
124 brcm,nand-oob-sector-size:
127 expected for the ECC layout in use. This size, in
128 addition to the strength and step-size,
129 determines how the hardware BCH engine will lay
135 number of available options for its default ECC
140 - $ref: nand-controller.yaml#
141 - if:
145 const: brcm,nand-bcm63138
148 reg-names:
150 - const: nand
151 - const: nand-int-base
152 - if:
156 const: brcm,nand-bcm6368
159 reg-names:
161 - const: nand
162 - const: nand-int-base
163 - const: nand-cache
164 - if:
168 const: brcm,nand-iproc
171 reg-names:
173 - const: nand
174 - const: iproc-idm
175 - const: iproc-ext
180 - reg
181 - reg-names
182 - interrupts
185 - |
186 nand-controller@f0442800 {
187 compatible = "brcm,brcmnand-v7.0", "brcm,brcmnand";
190 reg-names = "nand", "flash-dma";
191 interrupt-parent = <&hif_intr2_intc>;
194 #address-cells = <1>;
195 #size-cells = <0>;
200 nand-on-flash-bbt;
201 nand-ecc-strength = <12>;
202 nand-ecc-step-size = <512>;
204 #address-cells = <1>;
205 #size-cells = <1>;
208 - |
209 nand-controller@10000200 {
210 compatible = "brcm,nand-bcm63168", "brcm,nand-bcm6368",
211 "brcm,brcmnand-v4.0", "brcm,brcmnand";
215 reg-names = "nand", "nand-int-base", "nand-cache";
216 interrupt-parent = <&periph_intc>;
219 clock-names = "nand";
221 #address-cells = <1>;
222 #size-cells = <0>;
227 nand-on-flash-bbt;
228 nand-ecc-strength = <1>;
229 nand-ecc-step-size = <512>;
231 #address-cells = <1>;
232 #size-cells = <1>;