Lines Matching +full:gcc +full:- +full:msm8994
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-msm.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
8 title: Qualcomm SDHCI controller (sdhci-msm)
11 - Bhupesh Sharma <bhupesh.sharma@linaro.org>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
24 - enum:
25 - qcom,apq8084-sdhci
26 - qcom,msm8226-sdhci
27 - qcom,msm8953-sdhci
28 - qcom,msm8974-sdhci
29 - qcom,msm8916-sdhci
30 - qcom,msm8992-sdhci
31 - qcom,msm8994-sdhci
32 - qcom,msm8996-sdhci
33 - qcom,msm8998-sdhci
34 - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0
35 - items:
36 - enum:
37 - qcom,qcs404-sdhci
38 - qcom,sc7180-sdhci
39 - qcom,sc7280-sdhci
40 - qcom,sdm630-sdhci
41 - qcom,sdm670-sdhci
42 - qcom,sdm845-sdhci
43 - qcom,sdx55-sdhci
44 - qcom,sdx65-sdhci
45 - qcom,sm6115-sdhci
46 - qcom,sm6125-sdhci
47 - qcom,sm6350-sdhci
48 - qcom,sm8150-sdhci
49 - qcom,sm8250-sdhci
50 - qcom,sm8450-sdhci
51 - const: qcom,sdhci-msm-v5 # for sdcc version 5.0
57 reg-names:
64 - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock
65 - description: SDC MMC clock, MCLK
66 - description: TCXO clock
67 - description: clock for Inline Crypto Engine
68 - description: SDCC bus voter clock
69 - description: reference clock for RCLK delay calibration
70 - description: sleep clock for RCLK delay calibration
72 clock-names:
75 - const: iface
76 - const: core
77 - const: xo
78 - const: ice
79 - const: bus
80 - const: cal
81 - const: sleep
86 interrupt-names:
88 - const: hc_irq
89 - const: pwr_irq
91 pinctrl-names:
94 - const: default
95 - const: sleep
97 pinctrl-0:
101 pinctrl-1:
108 qcom,ddr-config:
112 qcom,dll-config:
124 - description: data path, sdhc to ddr
125 - description: config path, cpu to sdhc
127 interconnect-names:
129 - const: sdhc-ddr
130 - const: cpu-sdhc
132 power-domains:
136 mmc-ddr-1_8v: true
138 mmc-hs200-1_8v: true
140 mmc-hs400-1_8v: true
142 bus-width: true
144 max-frequency: true
146 operating-points-v2: true
149 '^opp-table(-[a-z0-9]+)?$':
153 const: operating-points-v2
156 '^opp-?[0-9]+$':
158 - required-opps
161 - compatible
162 - reg
163 - clocks
164 - clock-names
165 - interrupts
168 - $ref: mmc-controller.yaml#
170 - if:
175 - qcom,sdhci-msm-v4
181 - description: Host controller register map
182 - description: SD Core register map
183 - description: CQE register map
184 - description: Inline Crypto Engine register map
185 reg-names:
188 - const: hc
189 - const: core
190 - const: cqhci
191 - const: ice
197 - description: Host controller register map
198 - description: CQE register map
199 - description: Inline Crypto Engine register map
200 reg-names:
203 - const: hc
204 - const: cqhci
205 - const: ice
210 - |
211 #include <dt-bindings/interrupt-controller/arm-gic.h>
212 #include <dt-bindings/clock/qcom,gcc-sm8250.h>
213 #include <dt-bindings/clock/qcom,rpmh.h>
214 #include <dt-bindings/power/qcom-rpmpd.h>
217 compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5";
222 interrupt-names = "hc_irq", "pwr_irq";
224 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
225 <&gcc GCC_SDCC2_APPS_CLK>,
227 clock-names = "iface", "core", "xo";
229 qcom,dll-config = <0x0007642c>;
230 qcom,ddr-config = <0x80040868>;
231 power-domains = <&rpmhpd SM8250_CX>;
233 operating-points-v2 = <&sdhc2_opp_table>;
235 sdhc2_opp_table: opp-table {
236 compatible = "operating-points-v2";
238 opp-19200000 {
239 opp-hz = /bits/ 64 <19200000>;
240 required-opps = <&rpmhpd_opp_min_svs>;
243 opp-50000000 {
244 opp-hz = /bits/ 64 <50000000>;
245 required-opps = <&rpmhpd_opp_low_svs>;
248 opp-100000000 {
249 opp-hz = /bits/ 64 <100000000>;
250 required-opps = <&rpmhpd_opp_svs>;
253 opp-202000000 {
254 opp-hz = /bits/ 64 <202000000>;
255 required-opps = <&rpmhpd_opp_svs_l1>;