Lines Matching +full:clock +full:- +full:delay
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: mmc-controller.yaml#
19 - const: ti,am654-sdhci-5.1
20 - const: ti,j721e-sdhci-8bit
21 - const: ti,j721e-sdhci-4bit
22 - const: ti,am64-sdhci-8bit
23 - const: ti,am64-sdhci-4bit
24 - const: ti,am62-sdhci
25 - items:
26 - const: ti,j7200-sdhci-8bit
27 - const: ti,j721e-sdhci-8bit
28 - items:
29 - const: ti,j7200-sdhci-4bit
30 - const: ti,j721e-sdhci-4bit
38 power-domains:
46 clock-names:
49 - const: clk_ahb
50 - const: clk_xin
52 sdhci-caps-mask: true
54 dma-coherent:
58 # Used to delay the data valid window and align it to the sampling clock.
62 ti,otap-del-sel-legacy:
63 description: Output tap delay for SD/MMC legacy timing
68 ti,otap-del-sel-mmc-hs:
69 description: Output tap delay for MMC high speed timing
74 ti,otap-del-sel-sd-hs:
75 description: Output tap delay for SD high speed timing
80 ti,otap-del-sel-sdr12:
81 description: Output tap delay for SD UHS SDR12 timing
86 ti,otap-del-sel-sdr25:
87 description: Output tap delay for SD UHS SDR25 timing
92 ti,otap-del-sel-sdr50:
93 description: Output tap delay for SD UHS SDR50 timing
98 ti,otap-del-sel-sdr104:
99 description: Output tap delay for SD UHS SDR104 timing
104 ti,otap-del-sel-ddr50:
105 description: Output tap delay for SD UHS DDR50 timing
110 ti,otap-del-sel-ddr52:
111 description: Output tap delay for eMMC DDR52 timing
116 ti,otap-del-sel-hs200:
117 description: Output tap delay for eMMC HS200 timing
122 ti,otap-del-sel-hs400:
123 description: Output tap delay for eMMC HS400 timing
129 # Used to delay the data valid window and align it to the sampling clock for
132 ti,itap-del-sel-legacy:
133 description: Input tap delay for SD/MMC legacy timing
138 ti,itap-del-sel-mmc-hs:
139 description: Input tap delay for MMC high speed timing
144 ti,itap-del-sel-sd-hs:
145 description: Input tap delay for SD high speed timing
150 ti,itap-del-sel-sdr12:
151 description: Input tap delay for SD UHS SDR12 timing
156 ti,itap-del-sel-sdr25:
157 description: Input tap delay for SD UHS SDR25 timing
162 ti,itap-del-sel-ddr52:
163 description: Input tap delay for MMC DDR52 timing
168 ti,trm-icp:
174 ti,driver-strength-ohm:
178 - 33
179 - 40
180 - 50
181 - 66
182 - 100
184 ti,strobe-sel:
185 description: strobe select delay for HS400 speed mode.
188 ti,clkbuf-sel:
189 description: Clock Delay Buffer Select
192 ti,fails-without-test-cd:
200 - compatible
201 - reg
202 - interrupts
203 - clocks
204 - clock-names
205 - ti,otap-del-sel-legacy
210 - |
211 #include <dt-bindings/interrupt-controller/irq.h>
212 #include <dt-bindings/interrupt-controller/arm-gic.h>
215 #address-cells = <2>;
216 #size-cells = <2>;
219 compatible = "ti,am654-sdhci-5.1";
221 power-domains = <&k3_pds 47>;
223 clock-names = "clk_ahb", "clk_xin";
225 sdhci-caps-mask = <0x80000007 0x0>;
226 mmc-ddr-1_8v;
227 ti,otap-del-sel-legacy = <0x0>;
228 ti,otap-del-sel-mmc-hs = <0x0>;
229 ti,otap-del-sel-ddr52 = <0x5>;
230 ti,otap-del-sel-hs200 = <0x5>;
231 ti,otap-del-sel-hs400 = <0x0>;
232 ti,itap-del-sel-legacy = <0x10>;
233 ti,itap-del-sel-mmc-hs = <0xa>;
234 ti,itap-del-sel-ddr52 = <0x3>;
235 ti,trm-icp = <0x8>;