Lines Matching +full:hs400 +full:- +full:ds +full:- +full:dly3
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
19 - enum:
20 - mediatek,mt2701-mmc
21 - mediatek,mt2712-mmc
22 - mediatek,mt6779-mmc
23 - mediatek,mt6795-mmc
24 - mediatek,mt7620-mmc
25 - mediatek,mt7622-mmc
26 - mediatek,mt8135-mmc
27 - mediatek,mt8173-mmc
28 - mediatek,mt8183-mmc
29 - mediatek,mt8516-mmc
30 - items:
31 - const: mediatek,mt7623-mmc
32 - const: mediatek,mt2701-mmc
33 - items:
34 - enum:
35 - mediatek,mt8186-mmc
36 - mediatek,mt8188-mmc
37 - mediatek,mt8192-mmc
38 - mediatek,mt8195-mmc
39 - const: mediatek,mt8183-mmc
44 - description: base register (required).
45 - description: top base register (required for MT8183).
52 - description: source clock (required).
53 - description: HCLK which used for host (required).
54 - description: independent source clock gate (required for MT2712).
55 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
56 - description: msdc subsys clock gate (required for MT8192).
57 - description: peripheral bus clock gate (required for MT8192).
58 - description: AXI bus clock gate (required for MT8192).
59 - description: AHB bus clock gate (required for MT8192).
61 clock-names:
64 - const: source
65 - const: hclk
66 - const: source_cg
67 - const: bus_clk
68 - const: sys_cg
69 - const: pclk_cg
70 - const: axi_cg
71 - const: ahb_cg
75 Should at least contain MSDC GIC interrupt. To support SDIO in-band wakeup, an extended
80 interrupt-names:
82 - const: msdc
83 - const: sdio_wakeup
85 pinctrl-names:
87 Should at least contain default and state_uhs. To support SDIO in-band wakeup, dat1 pin
92 - const: default
93 - const: state_uhs
94 - const: state_eint
96 pinctrl-0:
101 pinctrl-1:
106 pinctrl-2:
111 assigned-clocks:
116 assigned-clock-parents:
118 parent of source clock, used for HS400 mode to get 400Mhz source clock.
121 hs400-ds-delay:
124 HS400 DS delay setting.
128 mediatek,hs200-cmd-int-delay:
137 mediatek,hs400-cmd-int-delay:
140 HS400 command internal delay setting.
146 mediatek,hs400-cmd-resp-sel-rising:
149 HS400 command response sample selection.
150 If present, HS400 command responses are sampled on rising edges.
151 If not present, HS400 command responses are sampled on falling edges.
153 mediatek,hs400-ds-dly3:
156 Gear of the third delay line for DS for input data latch in data
161 value with corner IC and it is valid only for HS400 mode.
165 mediatek,latch-ck:
168 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
171 applied to compatible "mediatek,mt2701-mmc".
178 reset-names:
182 - compatible
183 - reg
184 - interrupts
185 - clocks
186 - clock-names
187 - pinctrl-names
188 - pinctrl-0
189 - pinctrl-1
190 - vmmc-supply
191 - vqmmc-supply
197 const: mediatek,mt8183-mmc
206 - |
207 #include <dt-bindings/interrupt-controller/irq.h>
208 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 #include <dt-bindings/clock/mt8173-clk.h>
211 compatible = "mediatek,mt8173-mmc";
214 vmmc-supply = <&mt6397_vemc_3v3_reg>;
215 vqmmc-supply = <&mt6397_vio18_reg>;
218 clock-names = "source", "hclk";
219 pinctrl-names = "default", "state_uhs";
220 pinctrl-0 = <&mmc0_pins_default>;
221 pinctrl-1 = <&mmc0_pins_uhs>;
222 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
223 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
224 hs400-ds-delay = <0x14015>;
225 mediatek,hs200-cmd-int-delay = <26>;
226 mediatek,hs400-cmd-int-delay = <14>;
227 mediatek,hs400-cmd-resp-sel-rising;
231 compatible = "mediatek,mt8173-mmc";
233 clock-names = "source", "hclk";
236 interrupt-names = "msdc", "sdio_wakeup";
237 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_LOW 0>,
239 pinctrl-names = "default", "state_uhs", "state_eint";
240 pinctrl-0 = <&mmc2_pins_default>;
241 pinctrl-1 = <&mmc2_pins_uhs>;
242 pinctrl-2 = <&mmc2_pins_eint>;
243 bus-width = <4>;
244 max-frequency = <200000000>;
245 cap-sd-highspeed;
246 sd-uhs-sdr104;
247 keep-power-in-suspend;
248 wakeup-source;
249 cap-sdio-irq;
250 no-mmc;
251 no-sd;
252 non-removable;
253 vmmc-supply = <&sdio_fixed_3v3>;
254 vqmmc-supply = <&mt6397_vgp3_reg>;
255 mmc-pwrseq = <&wifi_pwrseq>;