Lines Matching +full:mpfs +full:- +full:clock

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Masahiro Yamada <yamada.masahiro@socionext.com>
13   - $ref: mmc-controller.yaml
18       - enum:
19           - microchip,mpfs-sd4hc
20           - socionext,uniphier-sd4hc
21       - const: cdns,sd4hc
34   # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37   cdns,phy-input-delay-sd-highspeed:
38     description: Value of the delay in the input path for SD high-speed timing
43   cdns,phy-input-delay-legacy:
49   cdns,phy-input-delay-sd-uhs-sdr12:
55   cdns,phy-input-delay-sd-uhs-sdr25:
61   cdns,phy-input-delay-sd-uhs-sdr50:
67   cdns,phy-input-delay-sd-uhs-ddr50:
73   cdns,phy-input-delay-mmc-highspeed:
74     description: Value of the delay in the input path for MMC high-speed timing
79   cdns,phy-input-delay-mmc-ddr:
80     description: Value of the delay in the input path for eMMC high-speed DDR timing
82   # PHY DLL clock delays:
83   # Each delay property represents the fraction of the clock period.
90   cdns,phy-dll-delay-sdclk:
98   cdns,phy-dll-delay-sdclk-hsmmc:
106   cdns,phy-dll-delay-strobe:
115   - compatible
116   - reg
117   - interrupts
118   - clocks
123   - |
125         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
129         bus-width = <8>;
130         mmc-ddr-1_8v;
131         mmc-hs200-1_8v;
132         mmc-hs400-1_8v;
133         cdns,phy-dll-delay-sdclk = <0>;