Lines Matching full:delay

33   # They are used to delay the data valid window, and align the window to
34   # sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
37   cdns,phy-input-delay-sd-highspeed:
38     description: Value of the delay in the input path for SD high-speed timing
43   cdns,phy-input-delay-legacy:
44     description: Value of the delay in the input path for legacy timing
49   cdns,phy-input-delay-sd-uhs-sdr12:
50     description: Value of the delay in the input path for SD UHS SDR12 timing
55   cdns,phy-input-delay-sd-uhs-sdr25:
56     description: Value of the delay in the input path for SD UHS SDR25 timing
61   cdns,phy-input-delay-sd-uhs-sdr50:
62     description: Value of the delay in the input path for SD UHS SDR50 timing
67   cdns,phy-input-delay-sd-uhs-ddr50:
68     description: Value of the delay in the input path for SD UHS DDR50 timing
73   cdns,phy-input-delay-mmc-highspeed:
74     description: Value of the delay in the input path for MMC high-speed timing
79   cdns,phy-input-delay-mmc-ddr:
80     description: Value of the delay in the input path for eMMC high-speed DDR timing
83   # Each delay property represents the fraction of the clock period.
84   # The approximate delay value will be
85   # (<delay property value>/128)*sdmclk_clock_period.
90   cdns,phy-dll-delay-sdclk:
92       Value of the delay introduced on the sdclk output for all modes except
98   cdns,phy-dll-delay-sdclk-hsmmc:
100       Value of the delay introduced on the sdclk output for HS200, HS400 and
106   cdns,phy-dll-delay-strobe:
108       Value of the delay introduced on the dat_strobe input used in
133         cdns,phy-dll-delay-sdclk = <0>;