Lines Matching +full:feedback +full:- +full:pin
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Ulf Hansson <ulf.hansson@linaro.org>
20 - $ref: /schemas/arm/primecell.yaml#
21 - $ref: mmc-controller.yaml#
29 - arm,pl180
30 - arm,pl181
31 - arm,pl18x
33 - compatible
38 - description: The first version of the block, simply called
41 - const: arm,pl180
42 - const: arm,primecell
43 - description: The improved version of the block, found in the
48 - const: arm,pl181
49 - const: arm,primecell
50 - description: Wildcard entry that will let the operating system
54 - const: arm,pl18x
55 - const: arm,primecell
56 - description: Entry for STMicroelectronics variant of PL18x.
59 - const: st,stm32-sdmmc2
60 - const: arm,pl18x
61 - const: arm,primecell
72 dma-names:
74 - items:
75 - const: tx
76 - const: rx
77 - items:
78 - const: rx
79 - const: tx
81 power-domains: true
102 st,sig-dir-dat0:
104 description: ST Micro-specific property, bus signal direction pins used for
107 st,sig-dir-dat2:
109 description: ST Micro-specific property, bus signal direction pins used for
112 st,sig-dir-dat31:
114 description: ST Micro-specific property, bus signal direction pins used for
117 st,sig-dir-dat74:
119 description: ST Micro-specific property, bus signal direction pins used for
122 st,sig-dir-cmd:
124 description: ST Micro-specific property, CMD signal direction used for
125 pin CMD.
127 st,sig-pin-fbclk:
129 description: ST Micro-specific property, feedback clock FBCLK signal pin
132 st,sig-dir:
134 description: ST Micro-specific property, signal direction polarity used for
137 st,neg-edge:
139 description: ST Micro-specific property, data and command phase relation,
142 st,use-ckin:
144 description: ST Micro-specific property, use CKIN pin from an external
148 st,cmd-gpios:
151 The GPIO matching the CMD pin.
153 st,ck-gpios:
156 The GPIO matching the CK pin.
158 st,ckin-gpios:
161 The GPIO matching the CKIN pin.
164 st,cmd-gpios: [ "st,use-ckin" ]
165 st,ck-gpios: [ "st,use-ckin" ]
166 st,ckin-gpios: [ "st,use-ckin" ]
171 - compatible
172 - reg
173 - interrupts
176 - |
177 #include <dt-bindings/interrupt-controller/irq.h>
178 #include <dt-bindings/gpio/gpio.h>
183 interrupts-extended = <&vic 22 &sic 1>;
185 clock-names = "mclk", "apb_pclk";
188 - |
189 #include <dt-bindings/interrupt-controller/irq.h>
196 dma-names = "rx", "tx";
198 clock-names = "sdi", "apb_pclk";
199 max-frequency = <100000000>;
200 bus-width = <4>;
201 cap-sd-highspeed;
202 cap-mmc-highspeed;
203 cd-gpios = <&gpio2 31 0x4>;
204 st,sig-dir-dat0;
205 st,sig-dir-dat2;
206 st,sig-dir-cmd;
207 st,sig-pin-fbclk;
208 vmmc-supply = <&ab8500_ldo_aux3_reg>;
209 vqmmc-supply = <&vmmci>;
212 - |
217 clock-names = "mclk", "apb_pclk";
219 max-frequency = <400000>;
220 bus-width = <4>;
221 cap-mmc-highspeed;
222 cap-sd-highspeed;
223 full-pwr-cycle;
224 st,sig-dir-dat0;
225 st,sig-dir-dat2;
226 st,sig-dir-dat31;
227 st,sig-dir-cmd;
228 st,sig-pin-fbclk;
229 vmmc-supply = <&vmmc_regulator>;
232 - |
235 arm,primecell-periphid = <0x10153180>;
239 clock-names = "apb_pclk";
241 cap-sd-highspeed;
242 cap-mmc-highspeed;
243 max-frequency = <120000000>;