Lines Matching +full:lgm +full:- +full:clk
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: "mmc-controller.yaml#"
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
28 - xlnx,zynqmp-8.9a
29 - xlnx,versal-8.9a
32 clock-output-names:
34 - items:
35 - const: clk_out_sd0
36 - const: clk_in_sd0
37 - items:
38 - const: clk_out_sd1
39 - const: clk_in_sd1
44 - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY
45 - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY
46 - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY
47 - items:
48 - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY
49 - const: arasan,sdhci-5.1
52 arasan,soc-ctl-syscon.
53 - items:
54 - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY
55 - const: arasan,sdhci-8.9a
58 clock-output-names and '#clock-cells'.
59 - items:
60 - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY
61 - const: arasan,sdhci-8.9a
64 clock-output-names and '#clock-cells'.
65 - items:
66 - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY
67 - const: arasan,sdhci-5.1
70 arasan,soc-ctl-syscon.
71 - items:
72 - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY
73 - const: arasan,sdhci-5.1
76 arasan,soc-ctl-syscon.
77 - items:
78 - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
79 - const: arasan,sdhci-5.1
82 arasan,soc-ctl-syscon.
83 - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller
86 arasan,soc-ctl-syscon.
87 - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller
90 arasan,soc-ctl-syscon.
91 - items:
92 - const: intel,thunderbay-sdhci-5.1 # Intel Thunder Bay eMMC PHY
93 - const: arasan,sdhci-5.1
96 clock-output-names and '#clock-cells'.
105 clock-names:
108 - const: clk_xin
109 - const: clk_ahb
110 - const: gate
118 phy-names:
124 arasan,soc-ctl-syscon:
131 clock-output-names:
137 '#clock-cells':
144 xlnx,fails-without-test-cd:
151 xlnx,int-clock-stable-broken:
157 xlnx,mio-bank:
165 '#clock-cells': [ clock-output-names ]
168 - compatible
169 - reg
170 - interrupts
171 - clocks
172 - clock-names
177 - |
179 compatible = "arasan,sdhci-8.9a";
181 clock-names = "clk_xin", "clk_ahb";
183 interrupt-parent = <&gic>;
187 - |
189 compatible = "arasan,sdhci-5.1";
191 clock-names = "clk_xin", "clk_ahb";
193 interrupt-parent = <&gic>;
196 phy-names = "phy_arasan";
199 - |
200 #include <dt-bindings/clock/rk3399-cru.h>
201 #include <dt-bindings/interrupt-controller/arm-gic.h>
202 #include <dt-bindings/interrupt-controller/irq.h>
204 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
208 clock-names = "clk_xin", "clk_ahb";
209 arasan,soc-ctl-syscon = <&grf>;
210 assigned-clocks = <&cru SCLK_EMMC>;
211 assigned-clock-rates = <200000000>;
212 clock-output-names = "emmc_cardclock";
214 phy-names = "phy_arasan";
215 #clock-cells = <0>;
218 - |
220 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
221 interrupt-parent = <&gic>;
225 clock-names = "clk_xin", "clk_ahb";
226 clock-output-names = "clk_out_sd0", "clk_in_sd0";
227 #clock-cells = <1>;
228 clk-phase-sd-hs = <63>, <72>;
231 - |
233 compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
234 interrupt-parent = <&gic>;
238 clock-names = "clk_xin", "clk_ahb";
239 clock-output-names = "clk_out_sd0", "clk_in_sd0";
240 #clock-cells = <1>;
241 clk-phase-sd-hs = <132>, <60>;
244 - |
249 compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
251 interrupt-parent = <&ioapic1>;
255 clock-names = "clk_xin", "clk_ahb", "gate";
256 clock-output-names = "emmc_cardclock";
257 #clock-cells = <0>;
259 phy-names = "phy_arasan";
260 arasan,soc-ctl-syscon = <&sysconf>;
263 - |
267 compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
269 interrupt-parent = <&ioapic1>;
273 clock-names = "clk_xin", "clk_ahb", "gate";
274 clock-output-names = "sdxc_cardclock";
275 #clock-cells = <0>;
277 phy-names = "phy_arasan";
278 arasan,soc-ctl-syscon = <&sysconf>;
281 - |
285 compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
288 clock-names = "clk_xin", "clk_ahb";
292 phy-names = "phy_arasan";
293 assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
294 assigned-clock-rates = <200000000>;
295 clock-output-names = "emmc_cardclock";
296 #clock-cells = <0>;
297 arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
300 - |
304 compatible = "intel,keembay-sdhci-5.1-sd";
307 clock-names = "clk_xin", "clk_ahb";
310 arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
313 - |
318 compatible = "intel,thunderbay-sdhci-5.1", "arasan,sdhci-5.1";
323 clock-names = "clk_xin", "clk_ahb";
325 phy-names = "phy_arasan";
326 assigned-clocks = <&scmi_clk EMMC_XIN_CLK>;
327 clock-output-names = "emmc_cardclock";
329 #clock-cells = <0x0>;