Lines Matching +full:sgpio +full:- +full:port +full:- +full:ranges
1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ocelot Externally-Controlled Ethernet Switch
10 - Colin Foster <colin.foster@in-advantage.com>
17 The switch family is a multi-port networking switch that supports many
24 - mscc,vsc7512
29 "#address-cells":
32 "#size-cells":
35 spi-max-frequency:
39 "^pinctrl@[0-9a-f]+$":
41 $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml
43 "^gpio@[0-9a-f]+$":
45 $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml
49 - mscc,ocelot-sgpio
51 "^mdio@[0-9a-f]+$":
57 - mscc,ocelot-miim
60 - compatible
61 - reg
62 - '#address-cells'
63 - '#size-cells'
64 - spi-max-frequency
69 - |
70 ocelot_clock: ocelot-clock {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <125000000>;
77 #address-cells = <1>;
78 #size-cells = <0>;
82 spi-max-frequency = <2500000>;
84 #address-cells = <1>;
85 #size-cells = <1>;
88 compatible = "mscc,ocelot-miim";
89 #address-cells = <1>;
90 #size-cells = <0>;
93 sw_phy0: ethernet-phy@0 {
99 compatible = "mscc,ocelot-miim";
100 pinctrl-names = "default";
101 pinctrl-0 = <&miim1_pins>;
102 #address-cells = <1>;
103 #size-cells = <0>;
106 sw_phy4: ethernet-phy@4 {
112 compatible = "mscc,ocelot-pinctrl";
113 gpio-controller;
114 #gpio-cells = <2>;
115 gpio-ranges = <&gpio 0 0 22>;
118 sgpio_pins: sgpio-pins {
123 miim1_pins: miim1-pins {
130 compatible = "mscc,ocelot-sgpio";
131 #address-cells = <1>;
132 #size-cells = <0>;
133 bus-frequency = <12500000>;
135 microchip,sgpio-port-ranges = <0 15>;
136 pinctrl-names = "default";
137 pinctrl-0 = <&sgpio_pins>;
141 compatible = "microchip,sparx5-sgpio-bank";
143 gpio-controller;
144 #gpio-cells = <3>;
149 compatible = "microchip,sparx5-sgpio-bank";
151 gpio-controller;
152 #gpio-cells = <3>;