Lines Matching +full:zynq +full:- +full:ddrc +full:- +full:a05

1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Zynq A05 DDR Memory Controller
10   - Krzysztof Kozlowski <krzk@kernel.org>
11   - Manish Narani <manish.narani@xilinx.com>
12   - Michal Simek <michal.simek@xilinx.com>
15   The Zynq DDR ECC controller has an optional ECC support in half-bus width
16   (16-bit) configuration. It is cappable of correcting single bit ECC errors
21     const: xlnx,zynq-ddrc-a05
27   - compatible
28   - reg
33   - |
34     memory-controller@f8006000 {
35       compatible = "xlnx,zynq-ddrc-a05";