Lines Matching +full:memory +full:- +full:controller
1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Manish Narani <manish.narani@xilinx.com>
12 - Michal Simek <michal.simek@xilinx.com>
15 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
16 working with the memory devices supporting up to (LP)DDR4 protocol. It can
18 16-bits or 32-bits or 64-bits wide.
20 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
21 controller. It has an optional SEC/DEC ECC support in 64- and 32-bits
27 - deprecated: true
28 description: Synopsys DW uMCTL2 DDR controller v3.80a
29 const: snps,ddrc-3.80a
30 - description: Synopsys DW uMCTL2 DDR controller
31 const: snps,dw-umctl2-ddrc
32 - description: Xilinx ZynqMP DDR controller v2.40a
33 const: xlnx,zynqmp-ddrc-2.40a
37 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
39 Scrubber-Done signal, DFI Parity/CRC Error. Some platforms may have the
40 signals merged before they reach the IRQ controller or have some of them
45 interrupt-names:
49 - description: Common ECC CE/UE/Scrubber/DFI Errors IRQ
51 - const: ecc
52 - description: Individual ECC CE/UE/Scrubber/DFI Errors IRQs
61 A standard set of the clock sources contains CSRs bus clock, AXI-ports
67 clock-names:
79 reset-names:
86 - compatible
87 - reg
88 - interrupts
93 - |
94 #include <dt-bindings/interrupt-controller/arm-gic.h>
96 memory-controller@fd070000 {
97 compatible = "xlnx,zynqmp-ddrc-2.40a";
100 interrupt-parent = <&gic>;
102 interrupt-names = "ecc";
104 - |
105 #include <dt-bindings/interrupt-controller/irq.h>
107 memory-controller@3d400000 {
108 compatible = "snps,dw-umctl2-ddrc";
113 interrupt-names = "ecc_ce", "ecc_ue", "ecc_sbr", "dfi_e";
116 clock-names = "pclk", "aclk", "core", "sbr";