Lines Matching +full:clock +full:- +full:delay
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - enum:
16 - samsung,K3QF2F20DB
17 - const: jedec,lpddr3
19 '#address-cells':
28 - 4096
29 - 8192
30 - 16384
31 - 32768
33 io-width:
38 - 32
39 - 16
41 manufacturer-id:
48 revision-id:
49 $ref: /schemas/types.yaml#/definitions/uint32-array
57 '#size-cells':
61 tCKE-min-tck:
66 of clock cycles.
68 tCKESR-min-tck:
73 SELF REFRESH) in terms of number of clock cycles.
75 tDQSCK-min-tck:
79 DQS output data access time from CK_t/CK_c in terms of number of clock
82 tFAW-min-tck:
86 Four-bank activate window in terms of number of clock cycles.
88 tMRD-min-tck:
92 Mode register set command delay in terms of number of clock cycles.
94 tR2R-C2C-min-tck:
98 Additional READ-to-READ delay in chip-to-chip cases in terms of number
99 of clock cycles.
101 tRAS-min-tck:
105 Row active time in terms of number of clock cycles.
107 tRC-min-tck:
111 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
113 tRCD-min-tck:
117 RAS-to-CAS delay in terms of number of clock cycles.
119 tRFC-min-tck:
123 Refresh Cycle time in terms of number of clock cycles.
125 tRL-min-tck:
129 READ data latency in terms of number of clock cycles.
131 tRPab-min-tck:
135 Row precharge time (all banks) in terms of number of clock cycles.
137 tRPpb-min-tck:
141 Row precharge time (single banks) in terms of number of clock cycles.
143 tRRD-min-tck:
147 Active bank A to active bank B in terms of number of clock cycles.
149 tRTP-min-tck:
153 Internal READ to PRECHARGE command delay in terms of number of clock
156 tW2W-C2C-min-tck:
160 Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
161 of clock cycles.
163 tWL-min-tck:
167 WRITE data latency in terms of number of clock cycles.
169 tWR-min-tck:
173 WRITE recovery time in terms of number of clock cycles.
175 tWTR-min-tck:
179 Internal WRITE-to-READ command delay in terms of number of clock cycles.
181 tXP-min-tck:
185 Exit power-down to next valid command delay in terms of number of clock
188 tXSR-min-tck:
192 SELF REFRESH exit to next valid command delay in terms of number of clock
196 "^timings((-[0-9])+|(@[0-9a-f]+))?$":
197 $ref: jedec,lpddr3-timings.yaml
201 speed-bin. The user may provide the timings for as many speed-bins as is
205 - compatible
206 - density
207 - io-width
212 - |
216 io-width = <32>;
218 tCKE-min-tck = <2>;
219 tCKESR-min-tck = <2>;
220 tDQSCK-min-tck = <5>;
221 tFAW-min-tck = <5>;
222 tMRD-min-tck = <5>;
223 tR2R-C2C-min-tck = <0>;
224 tRAS-min-tck = <5>;
225 tRC-min-tck = <6>;
226 tRCD-min-tck = <3>;
227 tRFC-min-tck = <17>;
228 tRL-min-tck = <14>;
229 tRPab-min-tck = <2>;
230 tRPpb-min-tck = <2>;
231 tRRD-min-tck = <2>;
232 tRTP-min-tck = <2>;
233 tW2W-C2C-min-tck = <0>;
234 tWL-min-tck = <8>;
235 tWR-min-tck = <7>;
236 tWTR-min-tck = <2>;
237 tXP-min-tck = <2>;
238 tXSR-min-tck = <12>;
241 compatible = "jedec,lpddr3-timings";
242 max-freq = <800000000>;
243 min-freq = <100000000>;
248 tR2R-C2C = <0>;
257 tW2W-C2C = <0>;