Lines Matching +full:device +full:- +full:width
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
10 - Krzysztof Kozlowski <krzk@kernel.org>
15 - items:
16 - enum:
17 - elpida,ECB240ABACN
18 - elpida,B8132B2PB-6D-F
19 - enum:
20 - jedec,lpddr2-s4
21 - items:
22 - enum:
23 - jedec,lpddr2-s2
24 - items:
25 - enum:
26 - jedec,lpddr2-nvm
28 revision-id1:
32 Revision 1 value of SDRAM chip. Obtained from device datasheet.
33 Property is deprecated, use revision-id instead.
36 revision-id2:
40 Revision 2 value of SDRAM chip. Obtained from device datasheet.
41 Property is deprecated, use revision-id instead.
44 revision-id:
45 $ref: /schemas/types.yaml#/definitions/uint32-array
57 Density in megabits of SDRAM chip. Obtained from device datasheet.
59 - 64
60 - 128
61 - 256
62 - 512
63 - 1024
64 - 2048
65 - 4096
66 - 8192
67 - 16384
68 - 32768
70 io-width:
73 IO bus width in bits of SDRAM chip. Obtained from device datasheet.
75 - 32
76 - 16
77 - 8
79 tRRD-min-tck:
84 Obtained from device datasheet.
86 tWTR-min-tck:
90 Internal WRITE-to-READ command delay in terms of number of clock cycles.
91 Obtained from device datasheet.
93 tXP-min-tck:
97 Exit power-down to next valid command delay in terms of number of clock
98 cycles. Obtained from device datasheet.
100 tRTP-min-tck:
105 cycles. Obtained from device datasheet.
107 tCKE-min-tck:
111 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
112 of clock cycles. Obtained from device datasheet.
114 tRPab-min-tck:
119 Obtained from device datasheet.
121 tRCD-min-tck:
125 RAS-to-CAS delay in terms of number of clock cycles. Obtained from
126 device datasheet.
128 tWR-min-tck:
133 device datasheet.
135 tRASmin-min-tck:
139 Row active time in terms of number of clock cycles. Obtained from device
142 tCKESR-min-tck:
146 CKE minimum pulse width during SELF REFRESH (low pulse width during
147 SELF REFRESH) in terms of number of clock cycles. Obtained from device
150 tFAW-min-tck:
154 Four-bank activate window in terms of number of clock cycles. Obtained
155 from device datasheet.
158 "^lpddr2-timings":
159 $ref: jedec,lpddr2-timings.yaml
161 The lpddr2 node may have one or more child nodes of type "lpddr2-timings".
162 "lpddr2-timings" provides AC timing parameters of the device for
163 a given speed-bin. The user may provide the timings for as many
164 speed-bins as is required.
167 - compatible
168 - density
169 - io-width
174 - |
176 compatible = "elpida,ECB240ABACN", "jedec,lpddr2-s4";
178 io-width = <32>;
179 revision-id = <1 0>;
181 tRPab-min-tck = <3>;
182 tRCD-min-tck = <3>;
183 tWR-min-tck = <3>;
184 tRASmin-min-tck = <3>;
185 tRRD-min-tck = <2>;
186 tWTR-min-tck = <2>;
187 tXP-min-tck = <2>;
188 tRTP-min-tck = <2>;
189 tCKE-min-tck = <3>;
190 tCKESR-min-tck = <3>;
191 tFAW-min-tck = <8>;
193 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings0 {
194 compatible = "jedec,lpddr2-timings";
195 min-freq = <10000000>;
196 max-freq = <400000000>;
200 tRAS-min = <42000>;
206 tDQSCK-max = <5500>;
211 tRAS-max-ns = <70000>;
214 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings1 {
215 compatible = "jedec,lpddr2-timings";
216 min-freq = <10000000>;
217 max-freq = <200000000>;
221 tRAS-min = <42000>;
227 tDQSCK-max = <5500>;
232 tRAS-max-ns = <70000>;