Lines Matching +full:memory +full:- +full:controllers

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl353-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM PL353 Static Memory Controller (SMC) device-tree bindings
10   - Miquel Raynal <miquel.raynal@bootlin.com>
11   - Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com>
14   The PL353 Static Memory Controller is a bus where you can connect two kinds
15   of memory interfaces, which are NAND and memory mapped interfaces (such as
23         const: arm,pl353-smc-r2p1
25     - compatible
29     pattern: "^memory-controller@[0-9a-f]+$"
33       - const: arm,pl353-smc-r2p1
34       - const: arm,primecell
36   "#address-cells":
39   "#size-cells":
44       - description:
45           Configuration registers for the host and sub-controllers.
50       - description: clock for the memory device bus
51       - description: main clock of the SMC
53   clock-names:
55       - const: memclk
56       - const: apb_pclk
61       Memory bus areas for interacting with the devices. Reflects
62       the memory layout with four integer values following:
63       <cs-number> 0 <offset> <size>
65       - description: NAND bank 0
66       - description: NOR/SRAM bank 0
67       - description: NOR/SRAM bank 1
72   "@[0-3],[a-f0-9]+$":
76       bus. The controller can be a NAND controller or a pair of any memory
77       mapped controllers such as NOR and SRAM controllers.
82           Compatible of memory controller.
86           - items:
87               - description: |
88                   Chip-select ID, as in the parent range property.
91               - description: |
92                   Offset of the memory region requested by the device.
93               - description: |
94                   Length of the memory region requested by the device.
97       - compatible
98       - reg
101   - compatible
102   - reg
103   - clock-names
104   - clocks
105   - "#address-cells"
106   - "#size-cells"
107   - ranges
112   - |
113     smcc: memory-controller@e000e000 {
114       compatible = "arm,pl353-smc-r2p1", "arm,primecell";
116       clock-names = "memclk", "apb_pclk";
121       #address-cells = <2>;
122       #size-cells = <1>;
124       nfc0: nand-controller@0,0 {
125         compatible = "arm,pl353-nand-r2p1";
127         #address-cells = <1>;
128         #size-cells = <0>;