Lines Matching full:video

1 DT bindings for Xilinx video IP cores
4 Xilinx video IP cores process video streams by acting as video sinks and/or
6 creating a video pipeline.
8 Each video IP core is represented by an AMBA bus child node in the device
10 cores are represented as defined in ../video-interfaces.txt.
13 tree using bindings documented in ./xlnx,video.txt.
18 The following properties are common to all Xilinx video IP cores.
20 - xlnx,video-format: This property represents a video format transmitted on an
21   AXI bus between video IP cores, using its VF code as defined in "AXI4-Stream
22   Video IP and System Design Guide" [UG934]. How the format relates to the IP
25 - xlnx,video-width: This property qualifies the video format with the sample
29 - xlnx,cfa-pattern: When the video format is set to Mono/Sensor, this property