Lines Matching +full:vcodec +full:- +full:lat
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 +------------------------------------------------+-------------------------------------+
22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output |
24 +------------||-------------||-------------------+---------------------||--------------+
25 || lat || | core workqueue <parent>
26 -------------||-------------||-------------------|---------------------||---------------
27 ||<------------||----------------HW index---------------->|| <child>
29 +-------------------------------------------------------------+
32 | (lat/lat soc/core0/core1) |
33 +-------------------------------------------------------------+
38 There are two workqueues in parent device: lat workqueue and core workqueue. They are used
39 to lat and core hardware deocder. Lat workqueue need to get input bitstream and lat buffer,
40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
48 Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195
49 platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and
50 clock when lat start to work, don't have interrupt.
52 mt8195: lat soc HW + lat HW + core HW
53 mt8192: lat HW + core HW
58 - mediatek,mt8192-vcodec-dec
59 - mediatek,mt8186-vcodec-dec
60 - mediatek,mt8188-vcodec-dec
61 - mediatek,mt8195-vcodec-dec
79 dma-ranges:
84 "#address-cells":
87 "#size-cells":
94 '^vcodec-lat@[0-9a-f]+$':
100 - mediatek,mtk-vcodec-lat
101 - mediatek,mtk-vcodec-lat-soc
119 clock-names:
121 - const: sel
122 - const: soc-vdec
123 - const: soc-lat
124 - const: vdec
125 - const: top
127 assigned-clocks:
130 assigned-clock-parents:
133 power-domains:
137 - compatible
138 - reg
139 - iommus
140 - clocks
141 - clock-names
142 - assigned-clocks
143 - assigned-clock-parents
144 - power-domains
148 '^vcodec-core@[0-9a-f]+$':
153 const: mediatek,mtk-vcodec-core
171 clock-names:
173 - const: sel
174 - const: soc-vdec
175 - const: soc-lat
176 - const: vdec
177 - const: top
179 assigned-clocks:
182 assigned-clock-parents:
185 power-domains:
189 - compatible
190 - reg
191 - interrupts
192 - iommus
193 - clocks
194 - clock-names
195 - assigned-clocks
196 - assigned-clock-parents
197 - power-domains
202 - compatible
203 - reg
204 - iommus
205 - mediatek,scp
206 - dma-ranges
207 - ranges
214 - mediatek,mtk-vcodec-lat
218 - interrupts
223 - |
224 #include <dt-bindings/interrupt-controller/arm-gic.h>
225 #include <dt-bindings/memory/mt8192-larb-port.h>
226 #include <dt-bindings/interrupt-controller/irq.h>
227 #include <dt-bindings/clock/mt8192-clk.h>
228 #include <dt-bindings/power/mt8192-power.h>
231 #address-cells = <2>;
232 #size-cells = <2>;
235 video-codec@16000000 {
236 compatible = "mediatek,mt8192-vcodec-dec";
239 dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
240 #address-cells = <2>;
241 #size-cells = <2>;
244 vcodec-lat@10000 {
245 compatible = "mediatek,mtk-vcodec-lat";
261 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
262 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
263 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
264 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
267 vcodec-core@25000 {
268 compatible = "mediatek,mtk-vcodec-core";
287 clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
288 assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
289 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
290 power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;