Lines Matching +full:iommu +full:- +full:names
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-encoder.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Yunfei Dong <yunfei.dong@mediatek.com>
20 - mediatek,mt8173-vcodec-enc-vp8
21 - mediatek,mt8173-vcodec-enc
22 - mediatek,mt8183-vcodec-enc
23 - mediatek,mt8188-vcodec-enc
24 - mediatek,mt8192-vcodec-enc
25 - mediatek,mt8195-vcodec-enc
37 clock-names:
41 assigned-clocks: true
43 assigned-clock-parents: true
49 List of the hardware port in respective IOMMU block for current Socs.
50 Refer to bindings/iommu/mediatek,iommu.yaml.
52 dma-ranges:
55 Describes the physical address space of IOMMU maps to memory.
67 power-domains:
71 - compatible
72 - reg
73 - interrupts
74 - clocks
75 - clock-names
76 - iommus
77 - assigned-clocks
78 - assigned-clock-parents
81 - if:
86 - mediatek,mt8183-vcodec-enc
87 - mediatek,mt8192-vcodec-enc
91 - mediatek,scp
93 - if:
98 - mediatek,mt8173-vcodec-enc-vp8
99 - mediatek,mt8173-vcodec-enc
103 - mediatek,vpu
105 - if:
109 - mediatek,mt8173-vcodec-enc
110 - mediatek,mt8192-vcodec-enc
118 clock-names:
120 - const: venc_sel
127 clock-names:
129 - const: venc_lt_sel
134 - |
135 #include <dt-bindings/interrupt-controller/arm-gic.h>
136 #include <dt-bindings/clock/mt8173-clk.h>
137 #include <dt-bindings/memory/mt8173-larb-port.h>
138 #include <dt-bindings/interrupt-controller/irq.h>
141 compatible = "mediatek,mt8173-vcodec-enc";
144 iommus = <&iommu M4U_PORT_VENC_RCPU>,
145 <&iommu M4U_PORT_VENC_REC>,
146 <&iommu M4U_PORT_VENC_BSDMA>,
147 <&iommu M4U_PORT_VENC_SV_COMV>,
148 <&iommu M4U_PORT_VENC_RD_COMV>,
149 <&iommu M4U_PORT_VENC_CUR_LUMA>,
150 <&iommu M4U_PORT_VENC_CUR_CHROMA>,
151 <&iommu M4U_PORT_VENC_REF_LUMA>,
152 <&iommu M4U_PORT_VENC_REF_CHROMA>,
153 <&iommu M4U_PORT_VENC_NBM_RDMA>,
154 <&iommu M4U_PORT_VENC_NBM_WDMA>;
157 clock-names = "venc_sel";
158 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
159 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
163 compatible = "mediatek,mt8173-vcodec-enc-vp8";
166 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
167 <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
168 <&iommu M4U_PORT_VENC_BSDMA_SET2>,
169 <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
170 <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
171 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
172 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
173 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
174 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
177 clock-names = "venc_lt_sel";
178 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
179 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;