Lines Matching +full:one +full:- +full:to +full:- +full:one

1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Marek Szyprowski <m.szyprowski@samsung.com>
14   physical memory chunks visible as a contiguous region to DMA-capable peripheral
15   devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
17   System MMU is an IOMMU and supports identical translation table format to
20   another capabilities like L2 TLB or block-fetch buffers to minimize translation
23   System MMUs are in many to one relation with peripheral devices, i.e. single
24   peripheral device might have multiple System MMUs (usually one for each bus
25   master), but one System MMU can handle transactions from only one peripheral
26   device. The relation between a System MMU and the peripheral device needs to be
31   * MFC has one System MMU on its left and right bus.
32   * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34   * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
37   For information on assigning System MMU controller to its peripheral devices,
42     const: samsung,exynos-sysmmu
54   clock-names:
56       - items:
57           - const: sysmmu
58       - items:
59           - const: sysmmu
60           - const: master
61       - items:
62           - const: aclk
63           - const: pclk
65   "#iommu-cells":
68   power-domains:
70       Required if the System MMU is needed to gate its power.
71       Please refer to the following document:
72       Documentation/devicetree/bindings/power/pd-samsung.yaml
76   - compatible
77   - reg
78   - interrupts
79   - clocks
80   - clock-names
81   - "#iommu-cells"
86   - |
87     #include <dt-bindings/clock/exynos5250.h>
90       compatible = "samsung,exynos-sysmmu";
92       interrupt-parent = <&combiner>;
94       clock-names = "sysmmu", "master";
97       power-domains = <&pd_gsc>;
98       #iommu-cells = <0>;