Lines Matching +full:mt2701 +full:- +full:larb +full:- +full:port
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Yong Wu <yong.wu@mediatek.com>
16 ARM Short-Descriptor translation table format for address translation.
24 +--------+
26 gals0-rx gals1-rx (Global Async Local Sync rx)
29 gals0-tx gals1-tx (Global Async Local Sync tx)
31 +--------+
35 +----------------+-------
37 | gals-rx There may be GALS in some larbs.
40 | gals-tx
42 SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
46 +-----+-----+ +----+----+
48 | | |... | | | ... There are different ports in each larb.
59 Normally we specify a local arbiter(larb) for each multimedia HW
61 in each larb. Take a example, There are many ports like MC, PP, VLD in the
65 smi-common and m4u, and additional GALS module between smi-larb and
66 smi-common. GALS can been seen as a "asynchronous fifo" which could help
72 - enum:
73 - mediatek,mt2701-m4u # generation one
74 - mediatek,mt2712-m4u # generation two
75 - mediatek,mt6779-m4u # generation two
76 - mediatek,mt6795-m4u # generation two
77 - mediatek,mt8167-m4u # generation two
78 - mediatek,mt8173-m4u # generation two
79 - mediatek,mt8183-m4u # generation two
80 - mediatek,mt8186-iommu-mm # generation two
81 - mediatek,mt8192-m4u # generation two
82 - mediatek,mt8195-iommu-vdo # generation two
83 - mediatek,mt8195-iommu-vpp # generation two
84 - mediatek,mt8195-iommu-infra # generation two
86 - description: mt7623 generation one
88 - const: mediatek,mt7623-m4u
89 - const: mediatek,mt2701-m4u
99 - description: bclk is the block clock.
101 clock-names:
103 - const: bclk
110 $ref: /schemas/types.yaml#/definitions/phandle-array
117 Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
120 '#iommu-cells':
125 dt-binding/memory/mt2701-larb-port.h for mt2701 and mt7623,
126 dt-binding/memory/mt2712-larb-port.h for mt2712,
127 dt-binding/memory/mt6779-larb-port.h for mt6779,
128 dt-binding/memory/mt6795-larb-port.h for mt6795,
129 dt-binding/memory/mt8167-larb-port.h for mt8167,
130 dt-binding/memory/mt8173-larb-port.h for mt8173,
131 dt-binding/memory/mt8183-larb-port.h for mt8183,
132 dt-binding/memory/mt8186-memory-port.h for mt8186,
133 dt-binding/memory/mt8192-larb-port.h for mt8192.
134 dt-binding/memory/mt8195-memory-port.h for mt8195.
136 power-domains:
140 - compatible
141 - reg
142 - interrupts
143 - '#iommu-cells'
146 - if:
151 - mediatek,mt2701-m4u
152 - mediatek,mt2712-m4u
153 - mediatek,mt6795-m4u
154 - mediatek,mt8173-m4u
155 - mediatek,mt8186-iommu-mm
156 - mediatek,mt8192-m4u
157 - mediatek,mt8195-iommu-vdo
158 - mediatek,mt8195-iommu-vpp
162 - clocks
164 - if:
168 - mediatek,mt8186-iommu-mm
169 - mediatek,mt8192-m4u
170 - mediatek,mt8195-iommu-vdo
171 - mediatek,mt8195-iommu-vpp
175 - power-domains
177 - if:
182 - mediatek,mt2712-m4u
183 - mediatek,mt6795-m4u
184 - mediatek,mt8173-m4u
188 - mediatek,infracfg
190 - if: # The IOMMUs don't have larbs.
195 const: mediatek,mt8195-iommu-infra
199 - mediatek,larbs
204 - |
205 #include <dt-bindings/clock/mt8173-clk.h>
206 #include <dt-bindings/interrupt-controller/arm-gic.h>
209 compatible = "mediatek,mt8173-m4u";
213 clock-names = "bclk";
217 #iommu-cells = <1>;