Lines Matching +full:system +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
27 | . . | +-------+
28 +-------+ | . . |----->| IRQ |
29 | INTA |----------->| . . | +-------+
30 +-------+ | . +-----+ |
31 | +------+ | N | |
32 | | irqM | +-----+ |
33 | +------+ |
35 +----------------------+
38 Configuration of these MUXCNTL_N registers is done by a system controller
39 (like the Device Memory and Security Controller on K3 AM654 SoC). System
40 controller will keep track of the used and unused registers within the Router.
41 Driver should request the system controller to get the range of GIC IRQs
45 Communication between the host processor running an OS and the system
46 controller happens through a protocol called TI System Control Interface
51 const: ti,sci-intr
53 ti,intr-trigger-type:
64 interrupt-controller: true
66 '#interrupt-cells':
71 ti,interrupt-ranges:
72 $ref: /schemas/types.yaml#/definitions/uint32-matrix
78 - description: |
80 - description: |
82 - description: |
86 - compatible
87 - ti,intr-trigger-type
88 - interrupt-controller
89 - '#interrupt-cells'
90 - ti,sci
91 - ti,sci-dev-id
92 - ti,interrupt-ranges
97 - |
98 main_gpio_intr: interrupt-controller0 {
99 compatible = "ti,sci-intr";
100 ti,intr-trigger-type = <1>;
101 interrupt-controller;
102 interrupt-parent = <&gic500>;
103 #interrupt-cells = <1>;
105 ti,sci-dev-id = <131>;
106 ti,interrupt-ranges = <0 360 32>;