Lines Matching +full:interrupts +full:- +full:extended
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive Platform-Level Interrupt Controller (PLIC)
11 SiFive SoCs and other RISC-V SoCs include an implementation of the
12 Platform-Level Interrupt Controller (PLIC) high-level specification in
13 the RISC-V Privileged Architecture specification. The PLIC connects all
14 external interrupts in the system to all hart contexts in the system, via
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
21 Each interrupt can be enabled on per-context basis. Any context can claim
24 Each interrupt has a configurable priority. Higher priority interrupts are
25 serviced first. Each context can specify a priority threshold. Interrupts
29 The PLIC supports both edge-triggered and level-triggered interrupts. For
30 edge-triggered interrupts, the RISC-V PLIC spec allows two responses to edges
35 missing interrupts. This special handling is needed by at least the Renesas
36 RZ/Five SoC (AX45MP AndesCore with a NCEPLIC100) and the T-HEAD C900 PLIC.
38 While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
39 "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
41 SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
43 The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the
44 T-HEAD PLIC implementation requires setting a delegation bit to allow access
45 from S-mode. So add thead,c900-plic to distinguish them.
48 - Sagar Kadam <sagar.kadam@sifive.com>
49 - Paul Walmsley <paul.walmsley@sifive.com>
50 - Palmer Dabbelt <palmer@dabbelt.com>
55 - items:
56 - enum:
57 - renesas,r9a07g043-plic
58 - const: andestech,nceplic100
59 - items:
60 - enum:
61 - sifive,fu540-c000-plic
62 - starfive,jh7100-plic
63 - canaan,k210-plic
64 - const: sifive,plic-1.0.0
65 - items:
66 - enum:
67 - allwinner,sun20i-d1-plic
68 - const: thead,c900-plic
69 - items:
70 - const: sifive,plic-1.0.0
71 - const: riscv,plic0
78 '#address-cells':
81 '#interrupt-cells': true
83 interrupt-controller: true
85 interrupts-extended:
89 Specifies which contexts are connected to the PLIC, with "-1" specifying
91 riscv,cpu-intc node, which has a riscv node as parent.
96 Specifies how many external interrupts are supported by this controller.
100 power-domains: true
105 - compatible
106 - '#address-cells'
107 - '#interrupt-cells'
108 - interrupt-controller
109 - reg
110 - interrupts-extended
111 - riscv,ndev
114 - if:
119 - andestech,nceplic100
120 - thead,c900-plic
124 '#interrupt-cells':
129 '#interrupt-cells':
132 - if:
136 const: renesas,r9a07g043-plic
143 power-domains:
150 - clocks
151 - power-domains
152 - resets
157 - |
158 plic: interrupt-controller@c000000 {
159 #address-cells = <0>;
160 #interrupt-cells = <1>;
161 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
162 interrupt-controller;
163 interrupts-extended = <&cpu0_intc 11>,