Lines Matching +full:- +full:alike

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
10   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
11   - Geert Uytterhoeven <geert+renesas@glider.be>
15   interrupts of NMI, IRQ, and GPIOINT and the interrupts of the built-in peripheral
17     - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI interrupts
18     - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
19     - NMI edge select (NMI is not treated as NMI exception and supports fall edge and
20       stand-up edge detection interrupts)
23   - $ref: /schemas/interrupt-controller.yaml#
28       - enum:
29           - renesas,r9a07g044-irqc    # RZ/G2{L,LC}
30           - renesas,r9a07g054-irqc    # RZ/V2L
31       - const: renesas,rzg2l-irqc
33   '#interrupt-cells':
34     description: The first cell should contain external interrupt number (IRQ0-7) and the
38   '#address-cells':
41   interrupt-controller: true
52   clock-names:
54       - const: clk
55       - const: pclk
57   power-domains:
64   - compatible
65   - '#interrupt-cells'
66   - '#address-cells'
67   - interrupt-controller
68   - reg
69   - interrupts
70   - clocks
71   - clock-names
72   - power-domains
73   - resets
78   - |
79     #include <dt-bindings/interrupt-controller/arm-gic.h>
80     #include <dt-bindings/clock/r9a07g044-cpg.h>
82     irqc: interrupt-controller@110a0000 {
83             compatible = "renesas,r9a07g044-irqc", "renesas,rzg2l-irqc";
85             #interrupt-cells = <2>;
86             #address-cells = <0>;
87             interrupt-controller;
131             clock-names = "clk", "pclk";
132             power-domains = <&cpg>;