Lines Matching +full:mpm +full:- +full:pin +full:- +full:count

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/qcom,mpm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcom MPM Interrupt Controller
10   - Shawn Guo <shawn.guo@linaro.org>
14   MSM Power Manager (MPM) that is in always-on domain. In addition to managing
21   - $ref: /schemas/interrupt-controller.yaml#
26       - const: qcom,mpm
43   interrupt-controller: true
45   '#interrupt-cells':
48       The first cell is the MPM pin number for the interrupt, and the second
51   qcom,mpm-pin-count:
53       Specify the total MPM pin count that a SoC supports.
56   qcom,mpm-pin-map:
58       A set of MPM pin numbers and the corresponding GIC SPIs.
59     $ref: /schemas/types.yaml#/definitions/uint32-matrix
62         - description: MPM pin number
63         - description: GIC SPI number for the MPM pin
66   - compatible
67   - reg
68   - interrupts
69   - mboxes
70   - interrupt-controller
71   - '#interrupt-cells'
72   - qcom,mpm-pin-count
73   - qcom,mpm-pin-map
78   - |
79     #include <dt-bindings/interrupt-controller/arm-gic.h>
80     mpm: interrupt-controller@45f01b8 {
81         compatible = "qcom,mpm";
85         interrupt-controller;
86         #interrupt-cells = <2>;
87         interrupt-parent = <&intc>;
88         qcom,mpm-pin-count = <96>;
89         qcom,mpm-pin-map = <2 275>,