Lines Matching full:interrupt

4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13   This interrupt controller hardware is a second level interrupt controller that
14   is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17   Such an interrupt controller has the following hardware design:
19   - outputs multiple interrupts signals towards its interrupt controller parent
22     directly output an interrupt signal towards the interrupt controller parent,
23     or if they will output an interrupt signal at this 2nd level interrupt
30   - not all bits within the interrupt controller actually map to an interrupt
34   2nd level interrupt line		Outputs for the parent controller (e.g: ARM GIC)
36   0 -----[ MUX ] ------------|==========> GIC interrupt 75
39   1 -----[ MUX ] --------)---|==========> GIC interrupt 76
42   2 -----[ MUX ] --------)---|==========> GIC interrupt 77
48   7 ---------------------|---|===========> GIC interrupt 66
54                             |===========> GIC interrupt 64
65   - outputs a single interrupt signal to its interrupt controller parent
73   - $ref: /schemas/interrupt-controller.yaml#
88   interrupt-controller: true
90   "#interrupt-cells":
101       this 2nd level interrupt controller, and how they match their respective
102       interrupt parents. Should match exactly the number of interrupts
115       typically UARTs. Setting these bits will make their respective interrupt
116       outputs bypass this 2nd level interrupt controller completely; it is
117       completely transparent for the interrupt controller parent. This should
125   - interrupt-controller
126   - "#interrupt-cells"
131     irq0_intc: interrupt-controller@f0406800 {
133       interrupt-parent = <&intc>;
134       #interrupt-cells = <1>;
136       interrupt-controller;
143     irq1_intc: interrupt-controller@10000020 {
147        interrupt-controller;
148        #interrupt-cells = <1>;
149        interrupt-parent = <&cpu_intc>;