Lines Matching +full:interrupt +full:- +full:controller

1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
5 controller, or the HW block containing it, is referred to occasionally
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
14 - compatible : should be "brcm,bcm2835-armctrl-ic" or
15                  "brcm,bcm2836-armctrl-ic"
16 - reg : Specifies base physical address and size of the registers.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
19   interrupt source. The value shall be 2.
21   The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
25   The 2nd cell contains the interrupt number within the bank. Valid values
28 Additional required properties for brcm,bcm2836-armctrl-ic:
29 - interrupts : Specifies the interrupt on the parent for this interrupt
30   controller to handle.
32 The interrupt sources are as follows:
72 27: DMA11-14 - shared interrupt for DMA 11 to 14
73 28: DMAALL - triggers on all dma interrupts (including chanel 15)
115 intc: interrupt-controller {
116 	compatible = "brcm,bcm2835-armctrl-ic";
118 	interrupt-controller;
119 	#interrupt-cells = <2>;
123 intc: interrupt-controller {
124 	compatible = "brcm,bcm2836-armctrl-ic";
126 	interrupt-controller;
127 	#interrupt-cells = <2>;
129 	interrupt-parent = <&local_intc>;